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COP413C Datasheet(PDF) 11 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # COP413C
Description  Single-Chip CMOS Microcontrollers
PDF  16 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

COP413C Datasheet(HTML) 11 Page - National Semiconductor (TI)

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COP413C Instruction Set
Table II is a symbol table providing internal architecture in-
struction operand and operational symbols used in the in-
struction set table
Table III provides the mnemonic operand machine code
data flow skip conditions and description associated with
each instruction in the COP413C instruction set
TABLE II COP413C Instruction Set Table Symbols
Symbol
Definition
INTERNAL ARCHITECTURE SYMBOLS
A
4-bit Accumulator
B
6-bit RAM Address Register
Br
Upper 2 bits of B (register address)
Bd
Lower 4 bits of B (digit address)
C
1-bit Carry Register
EN
4-bit Enable Register
G
4-bit Register to latch data for G IO Port
L
8-bit TRI-STATE IO Port
M
4-bit contents of RAM Memory pointed to by B
Register
PC
9-bit ROM Address Register (program counter)
Q
8-bit Register to latch data for L IO Port
SA
9-bit Subroutine Save Register A
SB
9-bit Subroutine Save Register B
SIO
4-bit Shift Register and Counter
SK
Logic-Controlled Clock Output
Symbol
Definition
INSTRUCTION OPERAND SYMBOLS
d
4-bit Operand Field 0 – 15 binary (RAM Digit Select)
r
2-bit Operand Field 0 – 3 binary (RAM Register
Select)
a
9-bit Operand Field 0 – 511 binary (ROM Address)
y
4-bit Operand Field 0 – 15 binary (Immediate Data)
RAM(s) Contents of RAM location addressed by s
ROM(t) Contents of ROM location addressed by t
OPERATIONAL SYMBOLS
a
Plus
b
Minus
x
Replaces
Is exchanged with
e
Is equal to
A
The one’s complement of A
Z
Exclusive-OR
Range of values
TABLE III COP413C Instruction Set
Hex
Machine
Mnemonic
Operand
Code
Language Code
Data Flow
Skip Conditions
Description
(Binary)
ARITHMETIC INSTRUCTIONS
ASC
30
0011 0000
A a C a RAM(B)
x A Carry
Add with Carry Skip on
Carry
x C
Carry
ADD
31
0011 0001
A a RAM(B)
x A
None
Add RAM to A
AISC
y
5b
0101
y
A a y
x A
Carry
Add immediate Skip on
Carry (y i 0)
CLRA
00
0000 0000
0
x A
None
Clear A
COMP
40
0100 0000
A
x A
None
One’s complement of A to A
NOP
44
0100 0100
None
None
No Operation
RC
32
0011 0010
‘‘0’’
x C
None
Reset C
SC
22
0010 0010
‘‘1’’
x C
None
Set C
XOR
02
0000 0010
A Z RAM(B)
x A
None
Exclusive-OR RAM with A
11



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