MP2019 - 40V, 300mA, LOW QUIESCENT-CURRENT LINEAR REGULATOR

PRELIMINARY SPECIFICATIONS SUBJECT TO CHANGE

MP2019 Rev. 1.01

www.MonolithicPower.com

11

1/10/2018

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© 2018 MPS. All Rights Reserved.

OPERATION

The MP2019 is a linear regulator that supplies

power to systems with high-voltage batteries. It

includes a wide 3V to 40V input range, low

dropout voltage, and a low quiescent-supply

current (see Fig. 1).

The MP2019 provides a wide variety of fixed

output-voltage options: 1.8V, 1.9V, 2.3V, 2.5V,

3.0V, 3.3V, 3.45V, and 5.0V; also, it provides the

output-adjustable option (from 1.25V to 15V).

The output-adjustable version has an output that

is adjustable from 1.25V to 15V with a simple

resistor

divider.

It

uses

external

feedback,

allowing the user to set the output voltage with an

external resistor divider. The FB threshold is

1.25V, typically.

The IC enters shutdown mode when EN is low. In

shutdown mode, the pass transistor, control

circuitry, reference, and all biases turn off; this

reduces the supply current to <1µA. Connect EN

to VIN for automatic start-up.

The regulator output current is limited internally,

and the device is protected against short-circuit,

over-load, and over-temperature conditions (see

Fig. 2).

The peak output current is limited to around

1000mA,

which

exceeds

the

300mA

recommended continuous output current.

When the junction temperature is too high, the

thermal sensor sends a signal to the control logic

which shuts down the IC. The IC will re-start

when the temperature has cooled sufficiently.

The maximum power output current is a function

of the package’s maximum power dissipation for

a given temperature.

The maximum power dissipation is dependent on

the thermal resistance of the case and the circuit

board, the temperature difference between the

die junction and the ambient air, and the rate of

air flow. GND and the exposed pad must be

connected to the ground plane for proper

dissipation.

MP2019 has one power good (PG) pin. The PG

pin is the open drain of an internal MOSFET. It

source(<15V) through a resistor (i.e. 100kohm).

MOSFET turns off and PG pin is pulled to high by

drops to 88% of nominal value, the PG voltage is

pulled to GND.

There is a delay time when PG asserts high. The

delay time can be programmed by adding a

capacitor on PGDL. To select a capacitor for

PGDL, use below equation:

PGDL

PGDL

PGDL

th_PGDL

t

(ms) I

( A)

C

(nF)

V

(V)







Figure 2 shows the power good timing.

UVLO

Vreference

EA

EN

FB

GND

PG

PG

PGDL

For Fixed Output

Version Only

Figure 1. Functional Block Diagram