MP8762H datasheet(16/36 Pages) MPS

16 / 36 page

MP8762H ― 10A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER

MP8762H Rev. 1.2

www.MonolithicPower.com

6/21/2016

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

reasonable that the jitter in the skip mode is

larger. If one wants a system with less jitter

during ultra light load condition, the values of the

VFB resistors should not be too big, however, that

will decrease the light load efficiency.

Configuring the EN Control

En high to turn on the regulator and EN low to

turn it off. Do not float the pin.

For automatic start-up the EN pin can be pulled

up to input voltage through a resistive voltage

divider. Choose the values of the pull-up resistor

(RUP from VIN pin to EN pin) and the pull-down

resistor(RDOWN from EN pin to GND) to determine

the automatic start-up voltage:

)

(

)

(

DOWN

START

−

(11)

For example, for RUP=100k

and RDOWN=51k ,

the VIN-START is set at 4.44V.

To avoid noise, a 10nF ceramic capacitor from

EN to GND is recommended.

There is an internal zener diode on the EN pin,

which clamps the EN pin voltage to prevent it

from running away. The maximum pull up current

assuming a worst case 6V internal zener clamp

should be less than 1mA.

Therefore, when EN is driven by an external logic

signal, the EN voltage should be lower than 6V;

when EN is connected with VIN through a pull-up

resistor or a resistive voltage divider, the

resistance selection should ensure the maximum

pull up current less than 1mA.

If using a resistive voltage divider and VIN higher

than 6V, the allowed minimum pull-up resistor

RUP should meet the following equation:

DOWN

1mA

−

≤

(12)

Especially, just using the pull-up resistor RUP (the

pull-down resistor is not connected), the VIN-START

is determined by VCC UVLO, and the minimum

resistor value is:

( )

1mA

−

≥

Ω

(13)

A typical pull-up resistor is 100k .

External VCC bias

An external 5V VCC bias can disable the internal

LDO, in this case, Vin can be as low as 2.5V.

Soft Start

The

MP8762H

employs

soft

start

(SS)

mechanism to ensure smooth output during

power-up. When the EN pin becomes high, an

internal current source (20µA) charges up the SS

capacitor. The SS capacitor voltage takes over

the REF voltage to the PWM comparator. The

output voltage smoothly ramps up with the SS

voltage. Once the SS voltage reaches the same

level as the REF voltage, it keeps ramping up

while VREF takes over the PWM comparator. At

this point, the soft start finishes and it enters into

steady state operation.

The SS capacitor value can be determined as

follows:

(

)

(

)

(

)

( )

REF

(14)

If the output capacitors have large capacitance

value, it’s not recommended to set the SS time

too small. Otherwise, it’s easy to hit the current

limit during SS.

Pre-Bias Startup

The MP8762H has been designed for monotonic

startup into pre-biased loads. If the output is pre-

biased to a certain voltage during startup, the IC

will disable the switching of both high-side and

low-side switches until the voltage on the soft-

start capacitor exceeds

the sensed output

voltage at the FB pin.

Power Good (PG)

The MP8762H have power-good (PG) output.

The PG pin is the open drain of a MOSFET. It

should be connected to VCC or other voltage

source that is less 5.5V through a pull-up resistor

(e.g. 100k). After VCC is ready, the MOSFET is

turned on so that the PG pin is pulled to GND

before SS is ready. After FB voltage reaches

91% of REF voltage, the PG pin is pulled high

after a 2.5ms delay.

When the FB voltage drops to 80% of REF

voltage or exceeds 120% of the nominal REF

voltage, the PG pin will be pulled low.

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