MPQ4487 – STEP-DOWN CONVERTER WITH DUAL USB CHARGING PORTS, AEC-Q100

MPQ4487 Rev.1.0

www.MonolithicPower.com

21

10/17/2017

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ESD Protection for I/O Pins

Higher ESD levels should be considered for all

USB I/O pins. The MPQ4487 features high ESD

protection up to ±8kV human body model on

USB1 and USB2, and ±6kV human body model

on CC1 through CC4. The ESD structures can

withstand high ESD both in normal operation

and when the device is powered off. To further

extend CC's ESD level for covering complicated

application

environments,

additional

ESD

diodes can be added on CC.

Figure 11: Recommended CC Pins ESD

Enhancing

PCB Layout Guidelines

(10)

Efficient PCB layout is critical for stable

operation and thermal dissipation. For best

results, refer to Figure 12 and follow the

guidelines below.

1. Use short, direct, and wide traces to

connect OUT.

2. Add vias under the IC.

3. Route the OUT trace on both PCB layers.

4. Place the buck output ceramic capacitor

C2A and C2B on the left side and C2C on

the right side.

5. Add a large copper plane for PGND.

6. Add multiple vias to improve thermal

dissipation.

7. Connect AGND to PGND.

8. Place a large copper plane for SW, USB,

and USB2.

9. Route the USB1 and USB2 traces on both

PCB layers.

10. Add multiple vias.

11. Place

two

ceramic

input

decoupling

capacitors as close to IN and PGND as

possible to improve EMI performance.

side of the IC.

13. Place the BST capacitor close to BST and

SW.

14. Place the VCC decoupling capacitor as

close to VCC as possible.

NOTE:

10) The recommended layout is based on the Typical

Application Circuits in Figure 13 to Figure 15.