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MPQ6526 Datasheet(PDF) 8 Page - Monolithic Power Systems

Part # MPQ6526
Description  Hex Half-Bridge Motor Driver with Serial Input Control
PDF  19 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MPQ6526 Datasheet(HTML) 8 Page - Monolithic Power Systems

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MPQ6526 – HEX HALF-BRIDGE MOTOR DRIVER WITH SERIAL INPUT CONTROL
MPQ6526 Rev. 1.0
www.MonolithicPower.com
8
2/6/2017
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
SERIAL INTERFACE TIMING ELECTRICAL CHARACTERISTICS (7)
7V < VVS < 28V, VVCC = 5V, TJ = -40°C to +125°C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
Logic Inputs (DI, CLK, CS)
Input low-level threshold
0.3 x
VVCC
V
Input high-level threshold
0.7 x
VVCC
V
Pull-down current of DI, CLK
VDI, VCLK = VVCC
2
50
μA
Pull-up current of CS
VCS = 0V
2
50
μA
Logic Output (DO)
Output low level
0.5
V
Output high level
VVCC -
0.7V
V
Leakage current (tri-state)
0V < VDO < VVCC, VCS = VVCC
-10
10
μA
Timing Characteristics
DO enable after CS falling edge
T1
CDO = 100pF
200
ns
DO disable after CS rising edge
T2
CDO = 100pF
200
ns
DO falling/rising time
CDO = 100pF
100
ns
DO valid time
T10
CDO = 100pF
200
ns
CS set-up time (high to low)
T4
150
ns
CS set-up time (low to high)
T8
150
ns
CS high time
T9
Bit14 (SCT) = high
0.75
ms
Bit14 (SCT) = low
0.3
ms
CLK high time
T5
150
ns
CLK low time
T6
150
ns
CLK period time
333
ns
CLK set-up time (high to low)
T7
150
ns
CLK set-up time (low to high)
T3
150
ns
DI set-up time
T11
26
ns
DI hold time
T12
26
ns
NOTES:
6) Guaranteed by characterization, not tested in production.
7) Not subject to production test, specified by design.



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