SFH 5712

2010-03-31

3

Addressing for basic operation

I

• 1.8V IO-logic level for SDA and SCL

• IO-pins are open drain type and logic high level is set with external pull-up resistor

•SFH 5712-1/2 operates always as slave, address is 0x29 (7bits). Bit 0 is used to change between

Read (R/W bit =1) and Write mode (R/W bit =0)..

• Designed for the I

• see I

• Spikes up to 10 ns are suppressed on SDA & SCL

Address 0x29

Bit

7

6

5

4

3

2

1

0

Address

R/W bit

default

0

1

0

1

0

0

1

X

S Address 0x29 W

Communication from master to SFH 5712

Communication from SFH 5712 to master

W= Master writes

R = Master reads

A = acknowledge

LSB = least significant byte

Register 0x80

A

A

0x03

A P

S Address 0x29 W

Register 0x8C

A

A P

S Address 0x29 R

LSB DATA

A

NA P

S Address 0x29 W

Register 0x8D

A

A P

S Address 0x29 R

MSB DATA

A

NA P

S Address 0x29 W

Register 0x80

A

A

0x00

A P

NA= not acknowledge

S = START condition

P = STOP condition

MSB = most significant byte

S Address 0x29 W

Communication from master to SFH 5712

Communication from SFH 5712 to master

W= Master writes

R = Master reads

A = acknowledge

LSB = least significant byte

Register 0x80

A

A

0x03

A P

S Address 0x29 W

Register 0x8C

A

A P

S Address 0x29 R

LSB DATA

A

NA P

S Address 0x29 W

Register 0x8D

A

A P

S Address 0x29 R

MSB DATA

A

NA P

S Address 0x29 W

Register 0x80

A

A

0x00

A P

NA= not acknowledge

S = START condition

P = STOP condition

MSB = most significant byte