LTC3894 datasheet(21/32 Pages) LINER

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LTC3894

Rev 0

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Figure 7. Programmable Power Good UV

LTC3894

PGUV

VOUT

RUV2

RUV1

3894 F07

APPLICATIONS INFORMATION

a conventional power good cannot be used because 9V

is under the VFB UV threshold (12V – 10% or 10.8V).

In this example, the PGOOD window is defined between

10% above 12V and 10% below 9V. The Output Voltage

OV (VOUTOV) is 13.2V and Output Voltage UV (VOUTUV)

is 8.1V.

To set PGUV to trigger at 9V minus 10% or 8.1V use a

resistor divider as seen in Figure 7. The resistors RUV1

and RUV2 set the divided output to the PGUV pin. VOUTUV

is defined as the voltage where the divided output on the

PGUV pin is 0.72V (0.8V – 10%). The resistor divider may

be calculated as follows:

RUV(1,2) is chosen based on IQ current requirements.

RUV(1,2) = RUV1+RUV2 = Assume 500k

RUV1 = RUV(1,2) •

0.72V

VOUTUV

RUV1 = 500k •

0.72V

8.1

= 44k

RUV2 = RUV(1,2) –RUV1 = 500k – 44k = 456k, Use 453k

External N-Channel MOSFET Bias Path for the Gate

Driver (DRVUV/EXTG Pin and EXTS Pin)

The LTC3894 has an internal LDO to regulate the gate

driver bias voltage (VIN-CAP) to a nominal 8V and provide

the gate drive current. The amount of the gate current

depends on the external P-channel MOSFET gate capaci-

tance and switching frequency. Charging and discharging

the gate of the external P-channel MOSFET will result in an

effective gate drive current and power loss inside the chip.

For applications where a large gate drive current and

high VIN generate excessively high internal power dis-

sipation, the LTC3894 offers an option to bypass the

internal LDO with an external N-channel MOSFET. This

option will move the power dissipation off chip and lower

the internal chip temperature. To effectively keep the chip

and board temperature low, sufficient heat sink is required

for the N-channel MOSFET. The connections for the

N-channel MOSFET are shown in the Functional Diagram

on page 10. Connecting the N-channel MOSFET auto-

matically select the UVLO threshold of 6V. External buf-

fer resistor REXTG (1k) and ceramic bypass capacitors

CEXTS and CEXTG (0.1µF each, 20V rated) are required and

need to be placed as close as practical to the N-channel

MOSFET source terminal and EXTG pin respectively to

ensure stable operation.

External N-Channel MOSFET Selection

When selecting an external NMOS device for the external

gate driver charge path, threshold VGS(TH) ,maximum VDS

rating, and maximum power rating need to be considered

for the maximum VIN used in an application . A NMOS with

VGS(TH) less than 5V should be used. During operation,

the maximum continuous voltage drop across the external

N-channel MOSFET VDS can be calculated as:

VDS(EXT.NMOS) = VIN – 8V

The average current flowing through the NMOS can be

calculated as:

IAVG_NMOS = QG(ext. PFET) • f

where QG(ext. PFET) is the total Gate charge needed to turn

on the external PFET in a switching cycle, f is the switch-

ing frequency.

Total power dissipation in the N-channel MOSFET is:

PNMOS = VDS(EXT.NMOS) • IAVG_NMOS = (VIN – 8V) •

QG(ext. PFET) • f

As it can be seen, the maximum power dissipation occurs

at maximum VIN of 150V.

For example , in an application where VIN = 150V,

QG(ext. PFET) = 30nC, f = 350kHz, PNMOS = 142V • 30nC •

350kHz = 142V • 10.5mA = 1.49W

Sufficient heat sink is needed to remove the heat

generated.

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