TPS65014 datasheet(39/53 Pages) TI

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SERIAL INTERFACE

Data Line

Stable

Data Valid

Change

of Data

Allowed

DATA

CLK

START Condition

STOP Condition

DATA

CLK

TPS65014

SLVS551 – DECEMBER 2004

The serial interface is compatible with the standard and fast mode I

2C specifications, allowing transfers at up to

400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to

new values depending on the instantaneous application requirements and charger status to be monitored.

LSB set by the IFLSB pin; this allows the connection of two devices with the same address to the same bus. The

6 MSBs are 100100. Attempting to read data from register addresses not listed in this section results in FFh

being read out.

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are

reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable

whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start

condition and terminated with a stop condition. When addressed, the TPS65014 device generates an

acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra

clock pulse that is associated with the acknowledge bit. The TPS65014 device must pull down the DATA line

during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the

acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock

pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of

data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this

case, the slave TPS65014 device must leave the data line high to enable the master to generate the stop

condition.

The I

2C interface accepts data as soon as the voltage at V

CC is higher than the undervoltage lockout threshold

and one power rail of the converter (main, core, or one of the LDOs) is operating. Therefore, the I

2C interface is

not operating after applying the battery voltage as the device automatically enters the WAIT mode with all rails

off.

When the device is in WAIT mode, the I

2C registers are reset to their default values if all voltage rails are off. If

the device is in WAIT mode and one power rail is left on, the I

2C interface is operating and the registers are not

reset after leaving the WAIT mode.

Figure 39. Bit Transfer on the Serial Interface

Figure 40. START and STOP Conditions

TPS65014 Datasheet(PDF) 39 Page - Texas Instruments

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