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LTC7003 Datasheet(PDF) 4 Page - Linear Technology

Part # LTC7003
Description  Fast 60V Protected High Side NMOS Static Switch Driver
PDF  24 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

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LTC7003
4
7003f
For more information www.linear.com/LTC7003
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC7003 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC7003E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC7003I is guaranteed
over the –40°C to 125°C operating junction temperature range, the
LTC7003H is guaranteed over the –40°C to 150°C operating junction
temperature range and the LTC7003MP is tested and guaranteed over the
–55°C to 150°C operating junction temperature range.
High junction temperatures degrade operating lifetimes; operating lifetime is
derated for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors.
Note 3: The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according to
the formula:
TJ = TA + (PD • θJA), where θJA is 45°C/W.
Note 4: This IC includes over temperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Operation above the specified absolute maximum operating junction
temperature may impair device reliability or permanently damage the
device.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 6: For application concerned with pin creepage and clearance
distances at high voltages, the MSE16(12) variation package should be
used. See Applications Information.
Note 7: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only; otherwise permanent damage may
occur.
Note 8: Total supply current is the sum of the current into the VIN, SNS+
and SNS– pins.
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VSNS+ = 10V, VCC = VBST = 10V, VTS = GND = 0V,
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operation
VIH
VIL
Input Threshold Voltages
VINP Rising
VINP Falling
Hysteresis
l
l
1.7
1.3
2
1.6
400
2.2
1.8
V
V
mV
Input Pull-Down Resistance
VINP = 1V
1
MΩ
RUN and OVLO Pin Threshold Voltages
Rising
Falling
Hysteresis
1.16
1.05
1.21
1.10
110
1.26
1.15
V
V
mV
RUN and OVLO Leakage Current
VRUN = 1.3V, VOVLO = 1.3V
l
–100
0
100
nA
TIMER Threshold Voltage
VTIMER Rising to VFAULT Going Low
1.25
1.3
1.35
V
TIMER Early Warning Voltage
VFAULT Going Low to (TG-TS) Going Low
75
100
125
mV
TIMER Pin Fault Pull-Up Current
VTIMER = 1.0V, ISET = OPEN
l
–115
–100
–80
µA
TIMER Pin Pull-Down Current
VTIMER = 0.6V ISET = OPEN
ΔVSNS = 0mV
l
2.0
2.5
3.0
µA
FAULT Output Low Voltage
IFAULT = 1mA
l
0.2
0.5
V
FAULT Leakage Current
VFAULT = 5V
l
–100
0
100
nA
ΔVTH
Current Sense Threshold Voltage
ΔVSNS = (VSNS+ – VSNS–)
ISET = OPEN
VISET = 1.2V
VISET = 0V
l
22
54
15
30
60
20
36
64
24
mV
D
Retry Duty Cycle
ΔVSNS = 200mV
CTIMER = 1nF
l
0.06
0.1
%
ISET and VCCUV Pull-Up Current
VISET = 1.0V, VCCUV = 1.0V
–11.3
–10
–8.7
µA
IMON Output Voltage
ΔVSNS = 60mV, VTIMER = 0V, VINP = 3.5V
ΔVSNS = 30mV, VTIMER = 0V, VINP = 3.5V
l
1.12
1.2
0.6
1.28
V
V
Over-Current to TG Low Propagation Delay
ΔVSNS Step 10mV to 50mV, ISET = OPEN,
VTIMER = VCC, VINP = 3.5V
70
ns



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