LTC7813 datasheet(24/32 Pages) LINER

24 / 32 page

LTC7800

7800f

For more information www.linear.com/LTC7800

APPLICATIONS INFORMATION

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, VOUT shifts by an

amount equal to

ΔILOAD (ESR), where ESR is the effective

series resistance of COUT. ΔILOAD also begins to charge or

discharge COUT generating the feedback error signal that

forces the regulator to adapt to the current change and

return VOUT to its steady-state value. During this recov-

ery time VOUT can be monitored for excessive overshoot

or ringing, which would indicate a stability problem.

OPTI-LOOP compensation allows the transient response

to be optimized over a wide range of output capacitance

and ESR values. The availability of the ITH pin not only

allows optimization of control loop behavior, but it also

providesaDCcoupledandACfilteredclosed-loopresponse

test point. The DC step, rise time and settling at this test

point truly reflects the closed-loop response. Assuming a

predominantly second order system, phase margin and/

or damping factor can be estimated using the percentage

of overshoot seen at this pin. The bandwidth can also be

estimated by examining the rise time at the pin. The ITH

external components shown in Figure 9 circuit will provide

an adequate starting point for most applications.

The ITH series RC-CC filter sets the dominant pole-zero

loop compensation. The values can be modified slightly

to optimize transient response once the final PC layout is

done and the particular output capacitor type and value

have been determined. The output capacitors need to be

selected because the various types and values determine

the loop gain and phase. An output current pulse of 20%

to 80% of full-load current having a rise time of 1μs to

10μs will produce output voltage and ITH pin waveforms

that will give a sense of the overall loop stability without

breaking the feedback loop.

Placing a power MOSFET directly across the output ca-

pacitor and driving the gate with an appropriate signal

generator is a practical way to produce a realistic load step

condition. The initial output voltage step resulting from

the step change in output current may not be within the

bandwidth of the feedback loop, so this signal cannot be

used to determine phase margin. This is why it is better

to look at the ITH pin signal which is in the feedback loop

andisthefilteredandcompensatedcontrolloopresponse.

The gain of the loop will be increased by increasing RC

and the bandwidth of the loop will be increased by de-

creasing CC. If RC is increased by the same factor that

CC is decreased, the zero frequency will be kept the same,

thereby keeping the phase shift the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loopsystemandwilldemonstratetheactualoverall

supply performance.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUT, causing a rapid drop in VOUT. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

CLOAD to COUT is greater than 1:50, the switch rise time

should be controlled so that the load rise time is limited

to approximately 25 • CLOAD. Thus a 10μF capacitor would

require a 250μs rise time, limiting the charging current

to about 200mA.

Design Example

As a design example, assume VIN = 12V (nominal),

VIN = 22V (max), VOUT = 3.3V, IMAX = 5A, VSENSE(MAX)

= 75mV and f = 1MHz. The inductance value

is chosen first based on a 30% ripple current

assumption. The highest value of ripple current occurs

at the maximum input voltage. Tie the FREQ pin with a

54.9k resistor to GND, generating approximately 1MHz

operation. The inductor ripple current can be calculated

from the following equation:

ΔIL =

VOUT

( ) L()

1–

VOUT

VIN(NOM)













A 1.5μH inductor will produce 32% ripple current. The

peak inductor current will be the maximum DC value plus

one half the ripple current, or 5.8A. Increasing the ripple

current will also help ensure that the minimum on-time

of 45ns is not violated. The minimum on-time occurs at

maximum VIN:

tON(MIN) =

VOUT

VIN(MAX) f

( )

3.3V

22V 1MHz

(

)

= 150ns

LTC7813 Datasheet(PDF) 24 Page - Linear Technology

LTC7813 Datasheet(HTML) 24 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL