LTC3255 datasheet(16/28 Pages) LINER

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LTC7820

7820fc

For more information www.linear.com/LTC7820

APPLICATIONS INFORMATION

The value of the boost capacitors, CB1/CB2/CB3, needs

to be 100 times that of the total input capacitance of the

topside MOSFET(s). The standard 6.3V MLCC ceramic ca-

pacitors are good for CB1/CB2/CB3.Thereversebreakdown

of the external Schottky diodes must be greater than the

maximum operation voltage between the VLOW and GND

pins. When adjusting the gate drive level, the final arbiter

is the threshold voltage of the top MOSFET M1. The Top

driver voltage VCB1 has to be higher than the top FET M1

threshold voltage in all conditions. Logic level MOSFET

should be used, otherwise lower operating switching

frequency and lower forward voltage drop diodes are

necessary to raise the gate driver voltages.

Undervoltage Lockout

TheLTC7820hasaprecisionUVLOcomparatorconstantly

monitoring the INTVCC voltage to ensure that an adequate

gate-drive voltage is present. It locks out the switching

action when INTVCC is below 4.9V. To prevent oscillation

when there is a disturbance on INTVCC, the UVLO com-

parator has 200mV of precision hysteresis.

Another way to detect an undervoltage condition is to

monitor the input supply. Because the RUN pin has a pre-

cision turn-on reference of 1.22V, one can use a resistor

divider to the input to turn on the IC when the input volt-

age is high enough. An extra 5µA of current flows out of

the RUN pin once the RUN pin voltage passes 1.22V. One

can program the hysteresis of the RUN comparator by

adjusting the values of the resistive divider.

Fault Response and Timer Programming

The LTC7820 stops switching and pulls the FAULT pin

low during fault conditions. A capacitor connected from

the TIMER pin to GND sets the retry time to start-up if

fault conditions are removed. A typical waveform on the

TIMER pin during a fault condition is shown in Figure 5.

After the FAULT pin is pulled low, a 3.5µA pull-up current

flows out of TIMER pin and starts to charge the Timer

capacitor. The pull-up current increases to 7µA when the

TIMER pin voltage is higher than 0.5V and back to 3.5µA

when the TIMER pin voltage is higher than 1.2V. The

TIMER pin will be strongly pulled down whenever the

fault conditions are removed or the TIMER pin voltage is

higher than 4V. When the TIMER pin voltage is between

0.5V and 1.2V, the internal pre-balance circuit will source

or sink current to the VLOW pin and regulate the VLOW pin

to VHIGH_SENSE/2 with around 93mA/50mA capability. The

pre-balance time can be calculated based on the capacitor

CTIMER on the TIMER pin:

TPRE-BALANCE = CTIMER • 0.7V/7µA

So the pre-balance time is 100ms/µF (e.g. the pre-balance

time is 10ms with 0.1µF CTIMER).

For voltage divider applications, the output capacitors and

the flying capacitors are pre-balanced to half of the input

voltage during the startup. Assuming zero initial condi-

tions, the time to charge the capacitors, tCHARGE, can be

estimated from the equation:

tCHARGE = (COUT + CFLY) • VIN/2/93mA

7820 F05

FAULT

LOW

3.5µA CHARGE

TIMER PIN

3.5µA CHARGE

TIMER PIN

7µA CHARGE

TIMER PIN

0.5V

1.2V

PRE-BALANCE TIME

FAULT

RELEASE

Figure 5. Timer Behavior During Fault or Startup

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