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LTC2320-12

Rev B

For more information www.analog.com

APPLICATIONS INFORMATION

Total Harmonic Distortion (THD)

Totalharmonicdistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (fSMPL/2).

THD is expressed as:

THD = 20log

V22 + V32 + V42 + …+VN

where V1 is the RMS amplitude of the fundamental

frequency and V2 through VN are the amplitudes of the

second through Nth harmonics.

POWER CONSIDERATIONS

The LTC2320-12 requires two power supplies: the 3.3V

to 5V power supply (VDD), and the digital input/output

interface power supply (OVDD). The flexible OVDD supply

allows the LTC2320-12 to communicate with any digital

logic operating between 1.8V and 2.5V. When using LVDS

I/O, the OVDD supply must be set to 2.5V.

Power Supply Sequencing

The LTC2320-12 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2320-12

has a power-on-reset (POR) circuit that will reset the

LTC2320-12 at initial power-up or whenever the power

Figure 16. 32k Point FFT of the LTC2320-12

SNR = 78.4dB

THD = –90.9dB

SINAD = 78.2dB

SFDR = 95.2dB

FREQUENCY (MHz)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

–140

–120

–100

–80

–60

–40

–20

SMPL

232012 F16

supply voltage drops below 2V. Once the supply voltage

re-enters the nominal supply voltage range, the POR will

reinitialize the ADC. No conversions should be initiated

until 10ms after a POR event to ensure the reinitialization

period has ended. Any conversions initiated before this

time will produce invalid results.

TIMING AND CONTROL

CNV Timing

The LTC2320-12 sampling and conversion is controlled

by CNV. A rising edge on CNV will start sampling and the

fallingedgestartstheconversionandreadoutprocess.The

conversion process is timed by the SCK input clock. For

optimum performance, CNV should be driven by a clean

low jitter signal. The Typical Application at the back of the

data sheet illustrates a recommended implementation to

reduce the relatively large jitter from an FPGA CNV pulse

source. Note the low jitter input clock times the falling

edge of the CNV signal. The rising edge jitter of CNV is

much less critical to performance. The typical pulse width

of the CNV signal is 30ns with < 1.5ns rise and fall times

at a 1.5Msps conversion rate.

SCK Serial Data Clock Input

In SDR mode (SDR/DDR Pin 23 = GND), the falling edge

of this clock shifts the conversion result MSB first onto

the SDO pins. A 100MHz external clock must be applied at

Figure 17. Power Supply Current of the LTC2320-12

Versus Sampling Rate

VDD = 5V

VDD = 3.3V

SAMPLE FREQUENCY (Msps)

0.3

0.6

0.9

1.2

1.5

232012 F17

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