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LTC2320-12

Rev B

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APPLICATIONS INFORMATION

For example, the first conversion result on SDOA cor-

responds to analog input channel pair 1 and 2, followed

by the conversion results for channels 3 through 8. The

data output on SDOA then wraps back to channel 1 and

this pattern repeats indefinitely. Other SDO lanes follow a

similar circular pattern except the first conversion result

presented on each lane corresponds to its associated

analog input channel pairs (SDOA: analog inputs 1 and

2, SDOB: analog inputs 3 and 4, SDOC: analog inputs 5

and 6 and SDOD: analog inputs 7 and 8).

Applications that cannot accommodate the full four lanes

of serial data may employ fewer lanes without reconfigur-

ing the LTC2320-12. For example, capturing the first four

conversion results (64 SCK cycles total in SDR mode

and 64 SCK edges in DDR mode) from SDOA and SDOC

provides data for analog input channels 1 through 4, and

5 through 8, respectively, using two output lanes. If only

one lane can be accommodated, capturing the first eight

conversion results (128 SCK cycles total in SDR mode

and 128 SCK edges in DDR mode) from SDOA provides

data for all analog input channels. Generally, the more

data lanes used, the lower the required SCK frequency.

When using less than four lanes in LVDS mode, there is

a limit on the maximum possible conversion frequency.

See Table 3 for examples of various possibilities and the

resulting SCK frequency required.

BOARD LAYOUT

To obtain the best performance from the LTC2320-12,

a printed circuit board is recommended. Layout for the

printed circuit board (PCB) should ensure the digital and

analog signal lines are separated as much as possible.

In particular, care should be taken not to run any digital

clocks or signals adjacent to analog signals or underneath

the ADC.

Supply bypass capacitors should be placed as close as

possible to the supply pins. Low impedance common

returns for these bypass capacitors are essential to the

low noise operation of the ADC. A single solid ground

plane is recommended for this purpose. When possible,

screen the analog input traces using ground.

Recommended Layout

For a detailed look at the reference design for this con-

verter, including schematics and PCB layout, please refer

to DC2395A, the evaluation kit for the LTC2320-12.

Table 3. Conversion Frequency for Various I/O Modes

I/O MODE

CMOS/

LVDS PIN

SDR/

DDR PIN

SDO1 – 8

LANES

SDOA – D

LANES

SCK FREQ

(MHz)

CLKOUT FREQ

(MHz)

SCK

CYCLES

OVDD

CONVERSION

FREQUENCY

(Msps/CH)

CMOS

GND

(CMOS)

GND (SDR)

SDO1 – SDO8

100

1.8V to 2.5V

1.5

OVDD (DDR) SDO1 – SDO8

1.5

OVDD (DDR)

SDO1, SDO3,

SDO5, SDO7

1.25

GND (SDR)

SDO1

100

128

0.5

LVDS

OVDD

(LVDS)

GND (SDR)

SDOA – SDOD

200

2.5V

1.5

OVDD (DDR)

SDOA – SDOD

100

1.5

OVDD (DDR)

SDOA, SDOC

150

1.4

GND (SDR)

SDOA

300

128

1.0

Notes: Conversion Period (SDR) = tCNV_MIN + tCONV_MAX + (128/(Lanes • fSCK))

Conversion Period (DDR) = tCNV_MIN + tCONV_MAX + (64/(Lanes • fSCK))

Conversion Frequency = 1/Conversion Period

SCK Cycles (SDR) = 128/Lanes

SCK Cycles (DDR) = 64/Lanes

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