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LTC1955

sn1955 1955fs

Electrical Fault Detection

Several types of faults are detected by the LTC1955. They

include VCCA/VCCB undervoltage, VCCA/VCCB overcurrent,

CLK A/CLK B, RST A/RST B, C8A, C4A short circuit, card

removal during a transaction, failed answer to reset (ATR),

supply undervoltage or UNDERV and chip overtemperature.

To prevent false errors from plaguing the microcontroller,

the electrical faults are acted upon only after a 5

µs (min)

timeout period. Card removal during transaction faults

initiate the deactivation sequence immediately.

VCCA/VCCB under voltage faults are determined by com-

paring the actual output voltage with the internal reference

voltage. If the output is more than ~5% below its set point

for the entire timeout period, the fault is reported and the

deactivation sequence is initiated.

VCCA/VCCB overcurrent faults are detected by comparing

the output current of the LDOs with an internal reference

level. If the current of an LDO is more than 100mA (typ) for

the entire timeout period, the fault is reported and the

deactivation sequence is initiated.

CLK A/CLK B and RST A/RST B faults are detected by

comparing the outputs of these pins with their expected

signals. If the signal on a pin is incorrect for the entire

timeout period, the fault is reported and the deactivation

sequence is initiated.

The clock channels are a special case. Since they can have

a free running clock, the error indication is accumulated

over a longer period of time without being cleared. Even

though the clock may be running, an error will still be

detected.

An overtemperature fault is detected by sensing the junc-

tion temperature of the IC. If the junction temperature

exceeds approximately 150

°C for the entire timeout

period, the fault is reported by setting both fault bits (D4

and D12) and the deactivation sequence is initiated.

A card removal fault is determined as soon as the PRES A/

PRES B pin is high (for NC/NO = 0). Once this occurs the

fault is reported and the deactivation sequence is initiated.

If no card is present, and the application software attempts

to power up a card socket, an automatic fault will result on

that channel.

OPERATIO

Short circuits on the I/O A/I/O B lines will not be detected

by the fault detection hardware; however, a short circuit

from these lines to their respective VCCA/VCCB pins will be

compliant with the maximum current limits set by appli-

cable standards (<15mA).

Answer to Reset (ATR) Fault Detection

Answer to Reset faults are detected by an internal counter

that is started once the RST A/B line goes high. If the DATA

pin remains high for 40,000 clock cycles, the ATR fault bit

for a given channel is set in the serial port’s status register

(see Table 1) and the FAULT pin is brought low.

An ATR fault can not occur if the clock mode of a channel

is set to synchronous. ATR faults will only occur for

asynchronous smart cards.

ATR faults are cleared by bringing the RST A/B pin low for

the faulted channel. This will also clear the FAULT pin to

the Hi-Z state (assuming no other errors are causing

FAULT to be low).

An ATR fault will not automatically deactivate a card

channel. It is the application programmer’s responsibility

to check the status register for ATR faults and deactivate

the smart card channel in accordance with smart card

standards. Generally the application has 50ms (EMV

2.1.3.1, 2.1.3.2) from the 40,000th clock pulse to deacti-

vate the card. Once the LTC1955 receives the deactivation

command, it will shut down a card channel in less than

250

µs.

Using the FAULT Pin

The FAULT pin can be used as an interrupt to a

microcontroller. It is an open-drain output and generally

requires a pull-up resistor. The FAULT pin will go low when

either an electrical fault or an answer to reset fault occurs

on either channel. Thus there are four possible faults that

can cause it to indicate a problem. The serial port’s status

occured and on which channel. The FAULT pin is logically

equivalent to D4+D5+D12+D13 (see Table 1).

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