LTC1955 datasheet(14/20 Pages) LINER

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LTC1955

sn1955 1955fs

10kV ESD Protection

All smart card pins (CLK A/CLK B, RST A/RST B, I/O A/

I/O B, C4A, C8A and VCCA/VCCB) can withstand over 10kV

of human body model ESD in-situ. In order to ensure

proper ESD protection, careful board layout is required.

The PGND and SGND pins should be tied directly to a

ground plane. The VCCA/VCCB capacitors should be located

very close to the VCCA/VCCB pins and tied immediately to

the ground plane.

Capacitor Selection

Warning: A polarized capacitor such as tantalum or alumi-

num should never be used for the flying capacitor since its

voltage can reverse upon start up of the LTC1955. Low

ESR ceramic capacitors should always be used for the

flying capacitor.

A total of six capacitors are required to operate the

LTC1955. An input bypass capacitor is required at PVBATT,

SVBATT and DVCC. Output bypass capacitors are required

on each of the smart card VCCA/VCCB pins. A charge pump

flying capacitor is required from C+ to C– and a charge

storage capacitor is required on the charge pump out pin

CPO.

To prevent excessive noise spikes due to charge pump

operation, low ESR (equivalent series resistance) multi-

layer ceramic capacitors are strongly recommended.

There are several types of ceramic capacitors available

each having considerably different characteristics. For

example, X7R/X5R ceramic capacitors have excellent volt-

age and temperature stability but relatively low packing

density. Y5V ceramic capacitors have apparently higher

packing density but poor performance over their rated

voltage or temperature ranges. Under certain voltage and

temperature conditions, Y5V and X7R/X5R ceramic ca-

pacitors can be compared directly by case size rather than

specified value for a desired minimum capacitance.

Placement of the capacitors is critical for correct operation

of the LTC1955. Because the charge pump generates large

current steps, all of the capacitors should be placed as

close to the LTC1955 as possible. The low impedance

nature of multilayer ceramic chip capacitors will minimize

voltage spikes but only if the power path is kept very short

APPLICATIO S I FOR ATIO

(i.e., minimum inductance). The PVBATT/SVBATT nodes

should be especially well bypassed. The capacitor for this

node should be directly adjacent to the QFN package. The

CPO and flying capacitors should be very close as well. The

LTC1955 can tolerate more distance between the LDO

capacitors and the VCCA/B pins.

Figure 4 shows an example of a tight printed circuit board

using single layer copper. For best performance a multi-

layer board can be used and should employ a solid ground

plane on at least one layer.

The following capacitors are recommended for use with

the LTC1955:

Type

Value

Case Size

Murata P/N

CIN

X5R

4.7

µF

0805

GRM40-034 X5R 475K 6.3

CPO

CFLY

X5R

µF

0603

GRM39 X5R 105K 6.3

VCCA/B

CDVCC

X5R

0.1

µF

0402

GRM36 X5R 104K 10

VCCA

GND

VBATT

VCCB 1955 F04

Figure 4. Optimum Single Layer PCB Layout

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