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LTC2372-16

237216f

For more information www.linear.com/LTC2372-16

applicaTions inForMaTion

POWER CONSIDERATIONS

The LTC2372-16 provides two power supply pins: the 5V

power supply (VDD), and the digital input/output interface

power supply (OVDD). The flexible OVDD supply allows

the LTC2372-16 to communicate with any digital logic

operating between 1.8V and 5V, including 2.5V and 3.3V

systems.

Power Supply Sequencing

The LTC2372-16 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2372-16

has a power-on-reset (POR) circuit that will reset the

LTC2372-16 at initial power-up or whenever the power

supply voltage drops below 2V. Once the supply voltage

re-enters the nominal supply voltage range, the POR will

reinitialize the ADC. No conversions should be initiated

until 100ms after a POR event to ensure the reinitialization

period has ended. Any conversions initiated before this

time will produce invalid results.

TIMING AND CONTROL

CNV Timing

The LTC2372-16 conversion is controlled by CNV. A ris-

ing edge on CNV will start a conversion and power up

the LTC2372-16. Once a conversion has been initiated,

it cannot be restarted until the conversion is complete.

For optimum performance, CNV should be driven by a

clean low jitter signal. Converter status is indicated by the

BUSY output which remains high while the conversion is

in progress. To ensure that no errors occur in the digitized

results, any additional transitions on CNV should occur

within 40ns from the start of the conversion or after the

conversion has been completed. Once the conversion

has completed, the LTC2372-16 powers down. It is not

necessary to clock out all of the data and configuration

bits before starting a new conversion.

Acquisition

AproprietarysamplingarchitectureallowstheLTC2372-16

to begin acquiring the input signal for the next conver-

sion 527ns after the start of the current conversion. This

extends the acquisition time to 1.460µs, easing settling

requirements and allowing the use of extremely low power

ADC drivers. (Refer to Timing Diagrams)

Internal Conversion Clock

The LTC2372-16 has an internal clock that is trimmed to

achieve a maximum conversion time of 1.5µs.

Auto Nap Mode

The LTC2372-16 automatically enters nap mode after a

conversion has been completed and completely powers

up once a new conversion is initiated on the rising edge of

CNV. During nap mode, only the ADC core powers down

and all other circuits remain active. During nap, data from

the last conversion can be clocked out. The auto nap mode

featurewillreducethepowerdissipationoftheLTC2372-16

as the sampling frequency is reduced. Since full power is

consumed only during a conversion, the ADC core of the

LTC2372-16remainspowereddownforalargerfractionof

the conversion cycle (tCYC) at lower sample rates, thereby

reducing the average power dissipation which scales with

the sampling rate as shown in Figure 16.

Sleep Mode

The auto nap mode feature provides limited power savings

since only the ADC core powers down. To obtain greater

power savings, the LTC2372-16 provides a sleep mode.

During sleep mode, the entire part is powered down

except for a small standby current resulting in a power

dissipation of 300μW. To enter sleep mode, toggle CNV

Figure 16. Power Supply Current of the LTC2372-16 vs

Sampling Rate

SAMPLING FREQUENCY (kHz)

237216 F16

100

200

300

400

500

IVDD

IOVDD

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