LT6236 datasheet(31/50 Pages) LINER

31 / 50 page

LTC2372-16

237216f

For more information www.linear.com/LTC2372-16

Figure 17. Changing the Configuration of the LTC2372-16 on Successive Conversions

and negative (−) channels are output at MUXOUT+ and

MUXOUT−, respectively.

Table 7. Channel Configuration

MUX CONFIGURATION

BITS

MULTIPLEXER CONFIGURATION

A[3] A[2] A[1] A[0] CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

–

Sequencer

The LTC2372-16 features a sequencer that can store up

to 16 7-bit control words in internal memory. The 7-bit

control word is defined in the Configuring the LTC2372-16

section. The sequencer repeatedly cycles through the

control words stored in sequencer memory on succes-

sive conversions if no new valid control words are input

to the part in a given transaction. The sequencer memory

is shown in Figure 18a.

An internal memory pointer determines which of the up

to 16 programmed control words is currently controlling

the converter. The pointer is reset to point to the first pro-

grammedcontrolwordeachtimethesequencermemoryis

programmed.Uponreachingthefinalprogrammedcontrol

word stored in memory, the pointer is automatically reset

to the first memory location and the sequence is restarted.

Atpower-uporafterresettingtheLTC2372-16,theinternal

sequencer memory programming defaults to a depth of 1

withcontrolwordC0[6:0]=0000000(CH0+/CH1–,unipolar

input range, digital gain compression disabled). Figure

18b shows the sequencer memory programmed with 8

configurations along with the memory pointer location for

conversions run after programming.

Start of Sequence

The start of sequence (SOS) bit is output to SDO on the

17th SCK cycle during all SPI transactions and indicates

whether the configuration for the conversion just per-

formed corresponds to the control word stored in the

first memory location of the sequencer memory. When

SOS=1, the current configuration corresponds to the first

memory location of the sequencer. The SOS bit can be

used to align the conversion data with the corresponding

control word when truncated SPI transactions are used

to maximize throughput. Only one extra bit needs to be

shifted out to maintain alignment of the configuration

with the conversion data. This results in needing 17 SCK

cycles instead of 24, which allows a higher throughput

to be achieved while being able to keep the configuration

information properly aligned with the conversion data.

applicaTions inForMaTion

MUXOUT–

MUXOUT+

V(CH1)

ADCIN–

ADCIN+

16-BIT

ADC CORE

R[1:0] = 10

FULLY DIFFERENTIAL

STRAIGHT BINARY

V(CH0)

CONVERSION #1

(+)

(–)

A[3:0] = 0000

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

MUX

MUXOUT–

MUXOUT+

CONVERSION #2

(+)

(–)

A[3:0] = 1010

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

MUX

237216 F17

V(COM)

ADCIN–

ADCIN+

16-BIT

ADC CORE

R[1:0] = 00

PSEUDO-DIFFERENTIAL

UNIPOLAR

V(CH2)

LT6236 Datasheet(PDF) 31 Page - Linear Technology

LT6236 Datasheet(HTML) 31 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL