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LTC4302CMS-2 Datasheet(PDF) 3 Page - Linear Technology

Part # LTC4302CMS-2
Description  Addressable 2-Wire Bus Buffers
PDF  20 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC4302CMS-2 Datasheet(HTML) 3 Page - Linear Technology

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LTC4302-1/LTC4302-2
3
sn430212 430212fs
ELECTRICAL CHARACTERISTICS
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 2.7V to 5.5V (LTC4302-1), VCC = VCC2 = 2.7V to 5.5V (LTC4302-2) unless otherwise noted.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The ICC tests are performed with the backplane-to-card connection
circuitry activated.
Note 3: When the GPIOs are in open-drain output or input mode, the logic
high voltage can be provided by a pull-up supply voltage ranging from
2.2V to 5.5V, independent of the VCC voltage.
Note 4: IPULLUP,AC varies with temperature and VCC voltage as shown in
the Typical Performance Characteristics section.
Note 5: The connection circuitry always regulates its output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pull-up resistor and V
CC voltage is shown in the Typical Performance
Characteristics section.
Note 6: The specifications in this section illustrate the LTC4302-1/
LTC4302-2’s compatibility with the I2C Fast Mode, the I2C Standard Mode
and SMBus specifications. See the Timing Diagram on page 5 for
illustrations of the timing parameters.
Note 7: CB = total capacitance of one bus line in pF.
Note 8: The digital interface circuit controls the data fall time only when
acknowledging or transmitting zeros during a read operation. The input-
output connection data and clock outputs meet the fall time specification
provided that the corresponding inputs meet the fall time specification.
Note 9: Guaranteed by design. Not subject to test.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
General Purpose I/Os
VLOW
I/O Logic Low Voltage
ISINK = 10mA, VCC = 2.7V
q
0.36
0.8
V
VHIGH
I/O Logic High Voltage
ISOURCE = 200µA, VCC = 2.7V
q
2.4
V
ILEAK
I/O Leakage Current
VI/O = 0V to 5.5V (Note 3)
q
±5
µA
VTHRESH
Input Threshold Voltage
Input Mode
q
0.8
1.5
2.2
V
Rise Time Accelerators
IPULLUP,AC Transient Boosted Pull-Up Current
Positive Transition on SDA, SCL,
q
12
mA
Slew Rate = 0.8V/
µs, VCC = 2.7V (Note 4)
Input-Output Connection
VOS
Output-Input Offset Voltage
10k to VCC on SDA, SCL Pins (Note 5),
q
0
100
175
mV
CIN
Digital Input Capacitance
(Note 9)
10
pF
VOL
Output Low Voltage
SDA, SCL Pins, ISINK = 3mA
q
0
0.4
V
ILEAK
Input Leakage Current
SDA, SCL Pins, VCC = 0V to 5.5V
q
±5
µA
Connection Circuits Inactive
2-Wire Digital Interface Voltage Characteristics
VLTH
Logic Threshold Voltage
q
0.3VCC 0.5VCC 0.7VCC
V
ILEAK
Digital Input Leakage
VCC = 0V to 5.5V
q
±5
µA
VOL
Digital Output Low Voltage
IPULLUP = 3mA Into SDAIN Pin
q
0.4
V
2-Wire Digital Interface Timing Characteristics (Note 6)
fI2C,MAX
I2C Operating Frequency
(Note 9)
400
600
kHz
tBUF
Bus Free Time Between Stop and Start
(Note 9)
0.75
1.3
µs
Condition
tHD,STA
Hold Time After (Repeated) Start Condition
(Note 9)
45
100
ns
tSU,STA
Repeated Start Condition Setup Time
(Note 9)
–30
0
ns
tSU,STO
Stop Condition Setup Time
(Note 9)
–30
0
ns
tHD,DATI
Data Hold Time Input
(Note 9)
–25
0
ns
tHD,DATO
Data Hold Time Output
300
600
900
ns
tSU,DAT
Data Setup Time
(Note 9)
50
100
ns
tSP
Pulse Width of Spikes Suppressed by
(Note 9)
50
150
250
ns
the Input Filter
tf
Data Fall Time
(Notes 7, 8, 9)
20 +
300
ns
0.1CB



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