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ICL232 Datasheet(PDF) 5 Page - Renesas Technology Corp |
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ICL232 Datasheet(HTML) 5 Page - Renesas Technology Corp |
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5 / 8 page ![]() ICL232 FN3020 Rev 8.00 Page 5 of 8 October 15, 2014 Detailed Description The ICL232 is a dual RS-232 transmitter/receiver powered by a single +5V power supply which meets all ElA RS232C specifications and features low power consumption. Figure 1 illustrates the major elements of the ICL232. The circuit is divided into three sections: a voltage doubler/inverter, dual transmitters, and dual receivers. Voltage Converter An equivalent circuit of the dual charge pump is illustrated in Figure 6. The voltage quadrupler contains two charge pumps which use two phases of an internally generated clock to generate +10V and -10V. The nominal clock frequency is 16kHz. During phase one of the clock, capacitor C1 is charged to VCC. During phase two, the voltage on C1 is added to VCC, producing a signal across C2 equal to twice VCC. At the same time, C3 is also charged to 2VCC, and then during phase one, it is inverted with respect to ground to produce a signal across C4 equal to -2VCC. The voltage converter accepts input voltages up to 5.5V. The output impedance of the doubler (V+) is approximately 200Ω, and the output impedance of the inverter (V-) is approximately 450Ω . Typical graphs are presented which show the voltage converters output vs input voltage and output voltages vs load characteristics. The test circuit (Figure 2) uses 1µF capacitors for C1 to C4, however, the value is not critical. Increasing the values of C1 and C2 will lower the output impedance of the voltage doubler and inverter, and increasing the values of the reservoir capacitors, C3 and C4, lowers the ripple on the V+ and V- supplies. Transmitters The transmitters are TTL/CMOS compatible inverters which translate the inputs to RS-232 outputs. The input logic threshold is about 26% of VCC , or 1.3V for VCC = 5V. A logic 1 at the input results in a voltage of between -5V and V- at the output, and a logic 0 results in a voltage between +5V and (V+ - 0.6V). Each transmitter input has an internal 400kΩ pullup resistor so any unused input can be left unconnected and its output remains in its low state. The output voltage swing meets the RS-232C specification of 5V minimum with the worst case conditions of: both transmitters driving 3kΩ minimum load impedance, VCC = 4.5V, and maximum allowable operating temperature. The transmitters have an internally limited output slew rate which is less than 30V/µs. The outputs are short circuit protected and can be shorted to ground indefinitely. The powered down output impedance is a minimum of 300Ω with 2V applied to the outputs and VCC = 0V. Receivers The receiver inputs accept up to 30V while presenting the required 3kΩ to 7kΩ input impedance even it the power is off (VCC = 0V). The receivers have a typical input threshold of 1.3V which is within the 3V limits, known as the transition region, of the RS-232 specification. The receiver output is 0V to VCC. The output will be low whenever the input is greater than 2.4V and high whenever the input is floating or driven between +0.8V and -30V. The receivers feature 0.5V hysteresis to improve noise rejection. Applications The ICL232 may be used for all RS-232 data terminal and communication links. It is particularly useful in applications where 12V power supplies are not available for conventional RS-232 interface circuits. The applications presented represent typical interface configurations. A simple duplex RS-232 port with CTS/RTS handshaking is illustrated in Figure 11. Fixed output signals such as DTR (data terminal ready) and DSRS (data signaling rate select) is generated by driving them through a 5kΩ resistor connected to V+. T1IN, T2IN T1OUT, T2OUT VOH VOL tr tf 90% 10% Instantaneous Slew Rate (SR) = (0.8) (VOH - VOL) tr or (0.8) (VOL - VOH) tf FIGURE 7. SLEW RATE DEFINITION TOUT V- < VTOUT < V+ 300Ω 400kΩ TXIN GND < TXIN < VCC V- V+ VCC FIGURE 8. TRANSMITTER ROUT GND < VROUT < VCC 5kΩ RXIN -30V < RXIN < +30V GND VCC FIGURE 9. RECEIVER T1IN, T2IN VOH VOL tPLH tPHL Average Propagation Delay = tPHL + tPLH 2 OR R1IN, R2IN T1OUT, T2OUT OR R1OUT, R2OUT FIGURE 10. PROPAGATION DELAY DEFINITION |
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