TLE9222 datasheet(21/43 Pages) INFINEON

21 / 43 page

Data Sheet

Rev. 1.2

2017-10-17

TLE9222

FlexRay Transceiver

Functional description

The RxEN flag indicates ongoing bus transmission. As soon as the bus state returns to idle, this flag is set

“high”.

The wake-up, power-on and error flags and their corresponding status register bits are latched “low”. A mode

change by host command or a correct SPI status bit register read-out will reset these flags, given that the error

condition has been resolved.

4.8.1

Read-out procedure

The SPI interface of the TLE9222 is enabled by the SCSN (SPI Chip Select Not) input. While SCSN is “high”, the

SDO (SPI Data Output) output is in a high impedance state and clock signals on the SCLK input are ignored.

The read-out procedure is initiated with a “low” signal on SCSN, which will cause the SDO output to be set

“low” (see Figure 13). After the time dSPILead the status register data can be shifted out on the SDO output

synchronized with the rising edge of a clock signal on the SCLK input. With a clock signal period of dSPIClk, the

TLE9222 supports SPI data rates in the range 10 kbit/s to 4 Mbit/sIf a transition on SCSN from “high” to “low”

is detected while SCLK is “high”, this would be identified as a SPI error.

Within the SCSN period, the time dSPISCSN_Low while the signal on SCSN is “low”, exactly 16 clock cycles are

expected for a correct read-out procedure. Incorrect SPI access, with more or less than 16 SCLK cycles or

wrong timing, is protected by the SPI timer. If the read-out time dSPISCSN_Low expires, the SDO output is set to

“high impedance” within the time dSPISDOZ. Additionally the error flag and SPI-error flag in the status register

will be set, while the state of all other latched bits are left unchanged.

Figure 14

SPI read-out

After a correct SPI read-out process, the information on the ERRN output and the flags in the status register

are refreshed. Next SPI read-out can be initiated after SCSN is set “high” for the time dSPIInterframe.

The SPI interface is available in both BD_Normal mode and BD_Standby mode, but SPI readout should not

occur at the same time as a mode change with the host interface, the time dBDModeChange must be respected.

The SPI register is also blocked during undervoltage conditions on VIO.

While the TLE9222 is set in BD_Standby with host command (pin STBN = “low”) and no wake-up or errors have

been detected, the SPI interface requires an enable time of dSPILeadStbOK from SCSN goes “low” until the first

rising edge on the clock signal on the SCLK input can be applied.

TLE9222_SPI_READ-OUT_V00

High

Low

High

Low

High

Low

High impedance

Bit 0

Bit 1

Bit 2

Bit 3

Bit 13

Bit 14

Bit 15

High impedance

dSPISCSN_Low

dSPILead

dSPILag

dSPIClk

dSPISDOZ

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