CMV2000 datasheet(14/64 Pages) AMSCO

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Reference: CMV2000-datasheet-v3.8

CMV2000 v3 Datasheet

Page 13 of 63

3 DRIVING THE CMV2000

3.1 SUPPLY SETTINGS

Supply

name

Usage

Recommended

value [V]

Range [V]

DC power

nominal [mW]

DC current

nominal [mA]

DC current

peak [mA]

VDD20

LVDS, ADC

2.0

2.0 - 2.2

640

300

VDD33

Dig. I\O, PGA, SPI, ADC

3.3

3.0 - 3.6

270

VDDPIX

Pixel array power supply

3.0

2.3 - 3.6

105

Vres_h

Pixel reset pulse

3.3

3.0 - 3.6

The power figures are measured at 48MHz CLK_IN speed in 16 channel mode while constantly grabbing images. When

idle, the sensor will consume about 25% less energy. Reducing the amount of output channels will reduce power

consumption of the VDD20 supply and will have the biggest impact on the power consumption.

All variations on the VDD33 and VDDPIX can contribute to variations (noise) on the analog pixel signal, which is seen as

noise in the image. During the camera design precautions have to be taken to supply the sensor with very stable supply

voltages to avoid this additional noise.

Because of the peak currents, decoupling is advised. Place large decoupling capacitors directly at the output of the

voltage regulator to filter low noise and improve peak current supply. We advise 1x 330µF electrolytic, 1x 33µF tantalum

and a 10µF ceramic capacitor per supply, directly at the output of the regulator.

Place small decoupling capacitors as close as possible to the sensor between supply pins and ground. We advise 1x 4.7µF

and 1x 100nF ceramic capacitor per power supply pin (see pin list) and 1x 100µF ceramic capacitor per power supply

plane (VDD20, VDDPIX, VDD33). Vres_h doesn’t need a 100µF capacitor. See pin list for exact pin numbers for every

supply. Analog and digital ground can be tied together.

3.2 BIASING

For optimal performance, some pins need to be decoupled to ground or to VDD. Please refer to the pin list for a detailed

description for every pin and the appropriate decoupling if applicable.

3.3 DIGITAL INPUT PINS

The table below gives an overview of the external pins used to drive the sensor. The digital signals are sampled on the

rising edge of the CLK_IN, therefor the length of the signal applied to an input should be at least 1 CLK_IN period to

assure it has been detected. All digital I/O’s have a capacitance of 2pF max.

Pin name

Description

CLK_IN

Master input clock, frequency range between 5 and 48 MHz

LVDS_CLK_N/P

High speed LVDS input clock, frequency range between 50 and 480 MHz. Should not be used

if PLL is enabled (default).

SYS_RES_N

System reset pin, active low signal. Resets the on-board sequencer and must be kept low

during start-up. This signal should be at least one period of CLK_IN to assure detection on the

rising edge of CLK_IN.

FRAME_REQ

Frame request pin. When a high level is detected on this pin the programmed number of

frames is captured and sent by the sensor. This signal should be at least one period of CLK_IN

to assure detection on the rising edge of CLK_IN.

SPI_IN

Data input pin for the SPI interface. The data to program the image sensor is sent over this pin.

SPI_EN

SPI enable pin. When this pin is high the data should be written/read on the SPI

SPI_CLK

SPI clock. This is the clock on which the SPI runs (max 48Mz)

T_EXP1

Input pin to program the exposure time externally. Optional

T_EXP2

Input pin to program the exposure time externally in HDR mode. Optional

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