TAS5142DDVR datasheet(20/26 Pages) TI

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THEORY OF OPERATION

POWER SUPPLIES

SYSTEM POWER-UP/POWER-DOWN

Powering Up

TAS5142

SLES126B – DECEMBER 2004 – REVISED MAY 2005

Special attention should be paid to the power-stage

power supply; this includes component selection,

PCB placement, and routing. As indicated, each

To facilitate system design, the TAS5142 needs only

half-bridge has independent power-stage supply pins

a 12-V supply in addition to the (typical) 32-V

(PVDD_X). For optimal electrical performance, EMI

power-stage supply. An internal voltage regulator

compliance, and system reliability, it is important that

provides suitable voltage levels for the digital and

each PVDD_X pin is decoupled with a 100-nF cer-

low-voltage analog circuitry. Additionally, all circuitry

amic capacitor placed as close as possible to each

requiring a floating voltage supply, e.g., the high-side

supply pin. It is recommended to follow the PCB

gate drive, is accommodated by built-in bootstrap

layout of the TAS5142 reference design. For ad-

circuitry requiring only a few external capacitors.

ditional information on recommended power supply

In order to provide outstanding electrical and acousti-

and required components, see the application dia-

cal characteristics, the PWM signal path including

grams given previously in this data sheet.

gate drive and output stage is designed as identical,

The 12-V supply should be from a low-noise,

independent half-bridges. For this reason, each

low-output-impedance voltage regulator. Likewise, the

half-bridge

has

separate

gate

drive

supply

32-V power-stage supply is assumed to have low

(GVDD_X), bootstrap pins (BST_X), and power-stage

output impedance and low noise. The power-supply

supply pins (PVDD_X). Furthermore, an additional pin

sequence is not critical as facilitated by the internal

(VDD) is provided as supply for all common circuits.

power-on-reset circuit. Moreover, the TAS5142 is fully

Although supplied from the same 12-V source, it is

protected against erroneous power-stage turnon due

highly

recommended

separate

GVDD_A,

to parasitic gate charging. Thus, voltage-supply ramp

GVDD_B, GVDD_C, GVDD_D, and VDD on the

rates (dV/dt) are non-critical within the specified

printed-circuit board (PCB) by RC filters (see appli-

range (see the Recommended Operating Conditions

cation diagram for details). These RC filters provide

section of this data sheet).

the recommended high-frequency isolation. Special

attention should be paid to placing all decoupling

capacitors as close to their associated pins as poss-

ible. In general, inductance between the power supply

SEQUENCE

pins and decoupling capacitors must be avoided.

(See reference board documentation for additional

information.)

The TAS5142 does not require a power-up sequence.

For a properly functioning bootstrap circuit, a small

The outputs of the H-bridges remain in a high-imped-

ceramic capacitor must be connected from each

ance

state

until

the

gate-drive

supply

voltage

bootstrap pin (BST_X) to the power-stage output pin

(GVDD_X)

and

VDD

voltage

are

above

the

(OUT_X). When the power-stage output is low, the

undervoltage protection (UVP) voltage threshold (see

bootstrap capacitor is charged through an internal

the Electrical Characteristics section of this data

diode connected between the gate-drive power--

sheet). Although not specifically required, it is rec-

supply pin (GVDD_X) and the bootstrap pin. When

ommended to hold RESET_AB and RESET_CD in a

the power-stage output is high, the bootstrap capaci-

low state while powering up the device. This allows

tor potential is shifted above the output potential and

an internal circuit to charge the external bootstrap

thus provides a suitable voltage supply for the

capacitors by enabling a weak pulldown of the

high-side gate driver. In an application with PWM

half-bridge output.

switching frequencies in the range from 352 kHz to

When the TAS5142 is being used with TI PWM

384 kHz, it is recommended to use 33-nF ceramic

modulators such as the TAS5508, no special atten-

capacitors, size 0603 or 0805, for the bootstrap

tion to the state of RESET_AB and RESET_CD is

supply. These 33-nF capacitors ensure sufficient

required, provided that the chipset is configured as

energy storage, even during minimal PWM duty

recommended.

cycles, to keep the high-side power stage FET

(LDMOS) fully turned on during the remaining part of

the PWM cycle. In an application running at a

reduced switching frequency, generally 192 kHz, the

bootstrap capacitor might need to be increased in

value.

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