TAS5142DDVR datasheet(21/26 Pages) TI

21 / 26 page

www.ti.com

Powering Down

Use

TAS5142

High-Modulation-Index

ERROR REPORTING

Overcurrent

(OC)

Protection

With

Current

DEVICE PROTECTION SYSTEM

TAS5142

SLES126B – DECEMBER 2004 – REVISED MAY 2005

overtemperature, and undervoltage. The TAS5142

responds to a fault by immediately setting the power

The TAS5142 does not require a power-down se-

stage in a high-impedance (Hi-Z) state and asserting

quence. The device remains fully operational as long

the SD pin low. In situations other than overload, the

as the gate-drive supply (GVDD_X) voltage and VDD

device automatically recovers when the fault con-

voltage are above the undervoltage protection (UVP)

dition has been removed, i.e., the junction tempera-

voltage threshold (see the Electrical Characteristics

ture has dropped or the supply voltage has in-

section of this data sheet). Although not specifically

creased. For highest possible reliability, recovering

required, it is a good practice to hold RESET_AB and

from an overload fault requires external reset of the

RESET_CD low during power down, thus preventing

device (see the Device Reset section of this data

audible artifacts including pops or clicks.

sheet) no sooner than 1 second after the shutdown.

When the TAS5142 is being used with TI PWM

modulators such as the TAS5508, no special atten-

Capable Systems

tion to the state of RESET_AB and RESET_CD is

required, provided that the chipset is configured as

This device requires at least 50 ns of low time on the

recommended.

output per 384-kHz PWM frame rate in order to keep

the bootstrap capacitors charged. As an example, if

the modulation index is set to 99.2% in the TAS5508,

this setting allows PWM pulse durations down to 20

The

and

OTW

pins

are

both

active-low,

ns. This signal, which does not meet the 50-ns

open-drain outputs. Their function is for protec-

requirement, is sent to the PWM_X pin and this

tion-mode signaling to a PWM controller or other

low-state pulse time does not allow the bootstrap

system-control device.

capacitor to stay charged. In this situation, the low

Any fault resulting in device shutdown is signaled by

voltage across the bootstrap capacitor can cause a

the SD pin going low. Likewise, OTW goes low when

failure of the high-side MOSFET transistor, especially

the device junction temperature exceeds 125

°C (see

when driving a low-impedance load. The TAS5142

the following table).

device requires limiting the TAS5508 modulation

index to 96.1% to keep the bootstrap capacitor

OTW

DESCRIPTION

charged under all signals and loads.

Overtemperature (OTE) or overload (OLP) or

undervoltage (UVP)

Therefore, TI strongly recommends using a TI PWM

Overload (OLP) or undervoltage (UVP)

processor, such as TAS5508 or TAS5086, with the

modulation index set at 96.1% to interface with

Junction temperature higher than 125°C

(overtemperature warning)

TAS5142.

Junction temperature lower than 125°C and no

OLP or UVP faults (normal operation)

Limiting and Overload Detection

Note that asserting either RESET_AB or RESET_CD

The device has independent, fast-reacting current

low forces the SD signal high, independent of faults

detectors with programmable trip threshold (OC

being present. TI recommends monitoring the OTW

threshold) on all high-side and low-side power-stage

signal using the system microcontroller and re-

FETs. See the following table for OC-adjust resistor

sponding to an overtemperature warning signal by,

values. The detector outputs are closely monitored by

e.g., turning down the volume to prevent further

two protection systems. The first protection system

heating of the device resulting in device shutdown

controls the power stage in order to prevent the

(OTE).

output current from further increasing, i.e., it performs

To reduce external component count, an internal

a current-limiting function rather than prematurely

pullup resistor to 3.3 V is provided on both SD and

shutting down during combinations of high-level mu-

OTW outputs. Level compliance for 5-V logic can be

sic transients and extreme speaker load impedance

obtained by adding external pullup resistors to 5 V

drops. If the high-current situation persists, i.e., the

(see the Electrical Characteristics section of this data

power stage is being overloaded, a second protection

sheet for further specifications).

system triggers a latching shutdown, resulting in the

power stage being set in the high-impedance (Hi-Z)

state. Current limiting and overload protection are

independent for half-bridges A and B and, respect-

The TAS5142 contains advanced protection circuitry

ively, C and D. That is, if the bridge-tied load between

carefully designed to facilitate system integration and

half-bridges A and B causes an overload fault, only

ease of use, as well as to safeguard the device from

half-bridges A and B are shut down.

permanent failure due to a wide range of fault

conditions

such

short

circuits,

overload,

TAS5142DDVR Datasheet(PDF) 21 Page - Texas Instruments

TAS5142DDVR Datasheet(HTML) 21 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL