TMS44409, TMS44409P

1048576-WORD BY 4-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SMHS563 – JULY1995

18

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

RAS

CAS

A0 – A9

W

OE

DQ1 – DQ4

Row

Column 1

Don’t Care

Valid

In 2

Column 2

tRASP

Valid

In 1

tRP

tCSH

tPRWC

tRCD

tCP

tCRP

tRSH

tASC

tCAH

tRAD

tASR

tCWD

tRAH

tAWD

tCWL

tRWL

tWP

tRWD

tCPA

tOEH

tDH

tDS

tAA

tRCS

tRAC

tCAC

tCLZ

tOEA

tOEZ

tOEH

tOED

tCAS

Valid Out 2

See Note A

Valid

Out 1

tCAL

tRAL

NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.

B. A read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not violated.

Figure 10. EDO Read-Write-Cycle Timing