VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8121

2.488GHz SONET/SDH

Clock Generator

Page 2

G52163-0, Rev 4.2

04/16/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Applications Information

High-Speed Clock Output

The differential clock output waveforms produced by the VSC8121 are sinusoidal in nature, by design. This

typically results in less noise generation than square pulses in most customer applications. Figure 1 shows a typ-

ical, single-ended clock output waveform produced by the device.

Figure 1: Typical Clock Output (CO) Waveform

CO and CON are high-speed CML outputs. As shown in Figure 2, the output driver consists of a differential

pair designed to drive a 50

Ω transmission line environment. Note that the output driver is back terminated to

50

Ω on-chip to prevent reflections.

Careful layout of these signals is required for optimal performance. Figure 3 demonstrates various termina-

tion methods that may be employed, depending on the particular application. Either DC-coupling (termination

#1 in Figure 3) or one of two AC coupling methods (terminations #2 and #3) may be used. As indicated, Vitesse

recommends termination #2 for AC-coupling.

100ps/div

75mV/div