W159
Document #: 38-07163 Rev. *A
Page 4 of 11
Maximum Allowed Current
Table 2. Maximum Allowed Current
Condition
Max. 2.5V supply consumption
Max. discrete cap loads,
VDDQ2=2.625V
All static inputs=VDDQ3 or VSS
Max. 3.3V supply consumption
Max. discrete cap loads,
VDDQ3=3.465V
All static inputs=VDDQ3 or VSS
Power-down Mode
(PWRDWN#=0)
300 µA
500 µA
Full Active 100 MHz
SEL133/100#=0
120 mA
160 mA
Full Active 133 MHz
SEL133/100#=1
120 mA
160 mA
Table 3. Clock Enable Configuration[2, 3, 4]
PWRDWN#
CPUCLK
CPUdiv2
APIC
3V66
3V33
48MHz
REF
OSC.
VCOs
0
LOW
LOW
LOW
LOW
LOW
LOW
LOW
OFF
OFF
1ON
ON
ON
ON
ON
ON
ON
ON
ON
Table 4. Power Management State Transition
Signal
Signal State
Latency[5]
PWRDWN#
1 (normal operation)
3 ms
0 (power down)
2 PCI clocks (max.)
Timing Diagram
PWRDWN# Timing Diagram[6, 7, 8, 9, 10]
Notes:
2.
LOW means outputs held static LOW as per latency requirement below.
3.
ON means active.
4.
PWRDWN# pulled LOW, impacts all outputs including REF and 48-MHz outputs.
5.
Power-up latency is when PWRDWN# goes inactive (HIGH) to when the first valid clocks are driven from the device.
6.
All internal timing is referenced to the CPUCLK.
7.
The internal label means inside the chip and is a reference only. This, in fact, may not be the way that the control is designed.
8.
PWRDWN is an asynchronous input and metastable conditions could exist. This signal is synchronized by the W159 internally.
9.
The shaded sections on the VCO and the Crystal signals indicate an active clock.
10. Diagrams shown with respect to 133 MHz. Similar operation when CPUCLK is 100 MHz.
CPUCLK
PCI
PWRDWN#
VCO
Crystal
PCI
CPUCLK
(internal)
(internal)
(external)
(external)
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