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W159 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # W159
Description  Spread Spectrum System FTG for SMP Systems
PDF  11 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

W159 Datasheet(HTML) 6 Page - Cypress Semiconductor

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W159
Document #: 38-07163 Rev. *A
Page 6 of 11
3.3V AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[17]
Notes:
14. X1 input threshold voltage (typical) is VDD/2.
15. The W159 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF;
this includes typical stray capacitance of short PCB traces to crystal.
16. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
17. Period, jitter, offset, and skew measured on rising edge at 1.5V.
18. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz.
Crystal Oscillator
VTH
X1 Input Threshold Voltage[14]
1.65
V
CLOAD
Load Capacitance, Imposed on
External Crystal[15]
18
pF
CIN,X1
X1 Input Capacitance[16]
Pin X2 unconnected
28
pF
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
Except X1 and X2
5
pF
COUT
Output Pin Capacitance
6
pF
LIN
Input Pin Inductance
7nH
3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency
Note 18
66.6
MHz
tH
High Time
Duration of clock cycle above 2.4V
4.95
ns
tL
Low Time
Duration of clock cycle below 0.4V
4.55
ns
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum dif-
ference of cycle time between two adjacent
cycles.
500
ps
tSK
Output Skew
Measured on rising edge at 1.5V
250
ps
tO
CPU to 3V66 Clock Skew
Covers all 3V66 outputs. Measured on rising
edge at 1.5V. CPU leads 3V66 outputs.
01.5
ns
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
15
Ω
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit



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