W159
Document #: 38-07163 Rev. *A
Page 7 of 11
Note:
19. 3V33 clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
3V33 Clock Outputs, 3V33_0:1 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
tP
Period
Measured on rising edge at 1.5V[19]
30
ns
tH
High Time
Duration of clock cycle above 2.4V
12
ns
tL
Low Time
Duration of clock cycle below 0.4V
12
ns
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum difference of
cycle time between two adjacent cycles.
500
ps
tSK
Output Skew
Measured on rising edge at 1.5V
500
ps
tO
3V66 to 3V33 Clock
Skew
Covers all 3V66 outputs. Measured on rising edge at 1.5V.
3V66 leads 3V33 output.
1.5
3.0
ns
tq
CPU to 3V33 Clock
Skew
Covers all 3V33 outputs. Measured on rising edge at 1.5V.
CPU leads 3V33 output.
1.5
4.0
ns
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used for deter-
mining series termination value.
15
Ω
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Frequency generated by crystal oscillator
14.318
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
25
Ω
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