EL4581

FN7172 Rev 2.00

Page 8 of 10

November 12, 2010

initiates the timing one-shots for gating the sample and hold

circuits. The sample of the sync tip is delayed by 0.8µs to

enable the actual sample of 2µs to be taken on the optimum

section of the sync. pulse tip. The acquisition time of the

circuit is about three horizontal lines. The double poly CMOS

technology enables long time constants to be achieved with

small high quality on-chip capacitors. The back porch

voltage is similarly derived from the trailing edge of sync,

which also serves to cut off the tip sample if the gate time

exceeds the tip period. Note that the sample and hold gating

The 50% level of the sync tip is derived, through the resistor

This comparator has built in hysteresis to avoid false

triggering. The output of C2 is a digital 5V signal which feeds

the C/S output buffer B1 and the other internal circuit blocks,

the vertical, back porch and odd/even functions.

The vertical circuit senses the C/S edges and initiates an

integrator which is reset by the shorter horizontal sync

pulses but times out the longer vertical sync. pulse widths.

the time-out period being inversely proportional to the timing

current. The vertical output pulse is started on the first

serration pulse in the vertical interval and is then self-timed

out. In the absence of a serration pulse, an internal timer will

default the start of vertical.

The back porch is triggered from the sync tip trailing edge

and initiates a one-shot pulse. The period of this pulse is

The odd/even circuit (O/E) comprises of flip flops which track

the relationship of the horizontal pulses to the leading edge

of the vertical output, and will switch on every field at the

start of vertical. Pin 7 is high during the odd field.

Loss of video signal can be detected by monitoring the C/S

output. The 50% level of the previous video signal will

remain held on the S/H capacitors after the input video

signal has gone and the input on pin 2 has defaulted to the

clamp voltage. Consequently, the C/S output will remain low

longer than the normal vertical pulse period. An external

timing circuit could be used to detect this condition.

Block Diagram

FIGURE 13. STANDARD (NTSC INPUT) H. SYNC DETAIL

*NOTE:

RSET MUST BE A

1% RESISTOR.

C SYNC OUT

1

A1

CLAMP

3-POLE FILTER

F1

2

VIDEO IN

C1

+

-

C2

CS

S/H

R1

R2

VTIP

VBP

VERTICAL

DETECT

R3

RSET

RSET

BACK

PORCH

DETECT

3

4

5

6

7

8

D2

B3

A2

-

+

B4

O/E

DETECT

ODD/EVEN

OUT

VERTICAL

OUT

GND

Q1

BURST/BACK

PORCH OUT

B1