HC5513 datasheet(15/20 Pages) RENESAS

15 / 20 page

HC5513

FN3963 Rev.12.00

Page 15 of 20

August 2003

SLIC Operating States

Notes

2. Overload Level (Two-Wire port) -

The overload level is specified

at the 2-wire port (VTR0) with the signal source at the 4-wire receive

port (ERX). IDCMET = 30A, increase the amplitude of ERX until 1%

THD is measured at VTRO. Reference Figure 1.

3. Longitudinal Impedance -

The longitudinal impedance is com-

puted using the following equations, where TIP and RING volt-

ages are referenced to ground. LZT, LZR, VT, VR, AR and AT are

defined in Figure 2.

(TIP) LZT = VT/AT

(RING) LZR = VR/AR

Where: EL = 1VRMS (0Hz to 100Hz).

4. Longitudinal Current Limit (Off-Hook Active) -

Off-Hook

(Active, C1 = 1, C2 = 0) longitudinal current limit is determined by

increasing the amplitude of EL (Figure 3A) until the 2-wire longitu-

dinal balance drops below 45dB. DET pin remains low (no false

detection).

5. Longitudinal Current Limit (On-Hook Standby) -

On-Hook

(Active, C1 = 1, C2 = 1) longitudinal current limit is determined by

increasing the amplitude of EL (Figure 3B) until the 2-wire longitudi-

nal balance drops below 45dB. DET pin remains high (no false

detection).

6. Longitudinal to Metallic Balance -

The longitudinal to metallic

balance is computed using the following equation:

BLME = 20

 log (EL/VTR), where: EL and VTR are defined in Fig-

ure 4.

7. Metallic to Longitudinal FCC Part 68, Para 68.310 -

The metal-

lic to longitudinal balance is defined in this spec.

8. Longitudinal to Four-Wire Balance -

The longitudinal to 4-wire

balance is computed using the following equation:

BLFE = 20

 log (EL/VTX),: EL and VTX are defined in Figure 4.

9. Metallic to Longitudinal Balance -

The metallic to longitudinal

balance is computed using the following equation:

BMLE = 20

 log (ETR/VL), ERX = 0

Where: ETR, VL and ERX are defined in Figure 5.

10. Four-Wire to Longitudinal Balance -

The 4-wire to longitudinal

balance is computed using the following equation:

BFLE = 20

 log (ERX/VL), ETR = source is removed.

Where: ERX, VL and ETR are defined in Figure 5.

11. Two-Wire Return Loss -

The 2-wire return loss is computed

using the following equation:

r = -20

 log (2VM/VS)

Where: ZD = The desired impedance; e.g., the characteristic

impedance of the line, nominally 600

(Reference Figure 6).

12. Overload Level (4-Wire port) -

The overload level is specified at

the 4-wire transmit port (VTXO) with the signal source (EG) at the

2-wire port, IDCMET = 23mA, ZL = 20k (Reference Figure 7).

Increase the amplitude of EG until 1% THD is measured at VTXO.

Note that the gain from the 2-wire port to the 4-wire port is equal to

13. Output Offset Voltage -

The output offset voltage is specified

with the following conditions: EG = 0, IDCMET = 23mA, ZL = 

and is measured at VTX. EG, IDCMET, VTX and ZL are defined in

Figure 7. Note: IDCMET is established with a series 600 resistor

between tip and ring.

TABLE 1. LOGIC TRUTH TABLE

SLIC OPERATING STATE

ACTIVE DETECTOR

DET OUTPUT

Open Circuit

No Active Detector

Logic Level High

Active

Ground Key Detector

Ground Key Status

Ringing

No Active Detector

Logic Level High

Standby

Ground Key Detector

Ground Key Status

Open Circuit

No Active Detector

Logic Level High

Active

Loop Current Detector

Loop Current Status

Ringing

Ring Trip Detector

Ring Trip Status

Standby

Loop Current Detector

Loop Current Status

Open Circuit

No Active Detector

Logic Level High

Active

Ground Key Detector

Ringing

No Active Detector

Standby

Ground Key Detector

Open Circuit

No Active Detector

Active

Loop Current Detector

Ringing

Ring Trip Detector

Standby

Loop Current Detector

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