CY2283
PRELIMINARY
6
Switching Characteristics for CY2283-1[9, 10]
Parameter
Output
Description
Test Conditions
Min.
Typ.
Max.
Unit
t1
All
Output Duty Cycle[11]
t1 = t1A ÷ t1B
45
50
55
%
t2
CPUCLK
CPU Clock Rising and
Falling Edge Rate
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.75
4.0
V/ns
t2
AGP,
REF0
AGP, REF0 Clock Rising
and Falling Edge Rate
Between 0.4V and 2.4V
0.85
4.0
V/ns
t2
PCI
PCI Rising and Falling
Edge Rate
Between 0.4V and 2.4V
0.85
4.0
V/ns
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.4
0.5
2.13
2.67
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V
Between 2.4V and 0.4V, VDDCPU = 3.3V
0.4
0.5
2.13
2.67
ns
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
Measured at 1.5V, VDDCPU = 3.3V
100
500
ps
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
2.5
3.5
5.5
ns
t8
PCICLK,
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
500
ps
t9
PCICLK,
AGP
PCI-AGP Clock Skew
Measured at 1.5V
1,200
ps
t10
CPUCLK
Cycle-Cycle Clock Jitter
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
500
ps
t10
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
750
ps
t10
AGP
Cycle-Cycle Clock Jitter
Measured at 1.5V
800
ps
t11
CPUCLK,
PCICLK,
AGP
Power-up Time
CPU, PCI, AGP clock stabilization from
power-up
3
ms
Notes:
9.
Guaranteed by Design and Characterization, not 100% tested in production.
10. Device characterized and parameters guaranteed with SDRAM outputs turned off. All other outputs at maximum load.
11. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDDCPU = 2.5V, CPUCLK duty cycle is measured at 1.25V.
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