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CY2283
PRELIMINARY
9
AGP-PCI Clock Skew
CPU_STOP[12, 13]
PCI_STOP[14, 15]
PWR_DOWN
Timing Requirements for the I2C Bus
Notes:
12. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles.
13. CPU_STOP may be applied asynchronously. It is synchronized internally.
14. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK.
15. PCI_STOP may be applied asynchronously. It is synchronized internally.
Switching Waveforms (continued)
AGPCLK
t9
PCICLK
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-Running)
CPU_STOP
CPUCLK
(External)
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
PCI_STOP
PCICLK
(External)
(Free-Running)
CPUCLK
(Internal)
PCICLK
(Internal)
PWR_DWN
PCICLK
CPUCLK
(External)
(External)
VCO
Crystal
Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
SDA
SCL
t13
t14
t15
t16
t17
t19
t20
t21
t22
t18
t14
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