PRELIMINARY
Pentium®/II, K6, 6x86 100-MHz Clock Synthesizer/Driver for
Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs
CY2283
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 12, 1998
Features
• Mixed 2.5V and 3.3V operation
• Complete clock solution for Pentium® /II, Cyrix 6x86,
and AMD K6 processor-based motherboards
— Four CPU clocks at 2.5V or 3.3V
— Twelve 3.3V SDRAM clocks[1]
— Five synchronous PCI clocks, one free-running
— One 3.3V 48 MHz USB clock
— One 3.3V Ref. clock at 14.318 MHz
— Two AGP clocks at 3.3V
• Support for ALI (-1 option) and VIA (-2 option)
•I2C™ Serial Configuration Interface
• Full EMI control with factory-EPROM programmable
output drive and slew rate
• Factory-EPROM programmable CPU clock frequencies
for custom configurations
• Power-down, CPU stop, and PCI stop pins
• Available in space-saving 48-pin SSOP package
Functional Description
The CY2283 is a clock Synthesizer/Driver for Pentium, Cyrix,
or AMD processor-based PCs using the ALI Aladdin V (-1 op-
tion) or VIA MVP3 (-2 option) chipset.
The CY2283 outputs four CPU clocks at 2.5V or 3.3V. There
are five PCI clocks, running at 30 or 33.3 MHz. One of the PCI
clocks is free-running. Additionally, the part outputs twelve
3.3V SDRAM clocks[1], one 3.3V USB clock at 48 MHz, and
one 3.3V reference clock at 14.318 MHz. Finally, the part out-
puts two AGP clocks running at 66.66 MHz or 60 MHz.
The CY2283 has the flexibility to work as either a one-chip or
as part of a two-chip clocking solution. In 100-MHz board de-
signs based on the ALI Aladdin V chipset, it is recommended
that the CY2283 be used with an external SDRAM buffer so-
lution such as the CY2318NZ or CY2314NZ. In this configura-
tion the SDRAM outputs on the CY2283 must be either turned
off using I2C or left floating. The CY231xNZ family provides the
SDRAM outputs in place of the CY2283 and can be placed in
close proximity to the SDRAM modules.
The CY2283 possesses power-down, CPU stop, and PCI stop
pins for power management control. These inputs are multi-
plexed with SDRAM clock outputs, and are selected when the
MODE pin is driven LOW. Additionally, the signals are synchro-
nized on-chip, and ensure glitch-free transitions on the out-
puts. When the CPU_STOP input is asserted, the CPU clock
outputs are driven LOW. When the PCI_STOP input is assert-
ed, the PCI clock outputs (except the free-running PCI clock)
are driven LOW. When the PWR_DWN pin is asserted, the
reference oscillator and PLLs are shut down, and all outputs
are driven LOW.
The CY2283 outputs are designed for low EMI emissions.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2283 Selector Guide
Notes:
1.
SDRAM clocks available up to 83.3MHz. In 100-MHz designs based on the
ALI V chipset, an external CY231xNZ buffer should be used.
2.
One free-running PCI clock
Clock Outputs
-1 (ALI V)
-2 (VIA MVP3)
CPU (66.6, 75, 83.3, 100MHz)
4
4
SDRAM
12[1]
12
PCI (30, 33.3 MHz)
5[2]
5[2]
USB (48MHz)
1
1
AGP (66.6, 60MHz)
2
2
Ref. (14.318 MHz)
1
1
CPU-PCI delay
2.5
−5.5 ns
2.5
−5.5 ns
AGP clock
In phase
with PCI
In phase
with CPU
Pin Configuration (48 SSOP)
Logic Block Diagram
EPROM
XTALOUT
XTALIN
14.318
MHz
OSC.
SDRAM [0-4],[8-11]
SEL0
SDRAM7/PCI_STOP
CPU
PLL
MODE
SCLK
SDATA
REF0 (14.318 MHz)
CPUCLK [0-3]
VDDCPU
SDRAM6/CPU_STOP
PCI [0-3]
PCICLK_F
STOP
STOP
LOGIC
LOGIC
SDRAM5/PWR_DWN
SEL1
USBCLK
SYS PLL
1
2
3
4
5
6
7
8
9
10
11
12
33
32
31
30
29
25
26
27
28
36
35
AVDD
34
13
14
15
16
17
18
19
20
21
22
23
24
45
44
43
42
41
37
38
39
40
48
47
46
REF0
VSS
XTALIN
XTALOUT
PCICLK_F
VDDQ3
PCICLK0
PCICLK1
VSS
PCICLK2
PCICLK3
AGP0
AGP1
VDDQ3
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
VSS
SDATA
SCLK
VDDQ3
USBCLK
SEL1
VSS
CPUCLK0
CPUCLK1
VDDCPU
CPUCLK2
CPUCLK3
VSS
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
VSS
SDRAM5/PWR_DWN
SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
VSS
SEL0
MODE
VDDQ3
SDRAM4
VSS
AGP
INTERFACE
CONTROL
LOGIC
SERIAL
Delay (-1 option)
/2
Delay (-2 option)
/1, /1.25, /1.5
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