ISL1221 datasheet(13/24 Pages) RENESAS

13 / 24 page

ISL1221

FN6316 Rev 1.00

Page 13 of 24

July 15, 2010

Real Time Clock Registers

Addresses [00h to 06h]

RTC REGISTERS (SC, MN, HR, DT, MO, YR, DW)

These registers depict BCD representations of the time. As

such, SC (Seconds) and MN (Minutes) range from 0 to 59, HR

(Hour) can either be a 12-hour or 24-hour mode, DT (Date) is 1

to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99, and DW

(Day of the Week) is 0 to 6.

The DW register provides a Day of the Week status and uses

three bits DW2 to DW0 to represent the seven days of the week.

The counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-…

The assignment of a numerical value to a specific day of the

week is arbitrary and may be decided by the system software

designer. The default value is defined as “0”.

24 HOUR TIME

If the MIL bit of the HR register is “1”, the RTC uses a 24-hour

format. If the MIL bit is “0”, the RTC uses a 12-hour format and

HR21 bit functions as an AM/PM indicator with a “1”

representing PM. The clock defaults to 12-hour format time

with HR21 = “0”.

LEAP YEARS

Leap years add the day February 29 and are defined as those

years that are divisible by 4. Years divisible by 100 are not leap

years, unless they are also divisible by 400. This means that the

year 2000 is a leap year, the year 2100 is not. The ISL1221 does

not correct for the leap year in the year 2100.

Control and Status Registers

Addresses [07h to 0Bh]

The Control and Status Registers consist of the Status

Digital Trimming Registers.

Status Register (SR)

The Status Register is located in the memory map at address

07h. This is a volatile register that provides either control or

status of RTC failure, battery mode, alarm trigger, event

detection, write protection of clock counter, crystal oscillator

enable and auto reset of status bits.

REAL TIME CLOCK FAIL BIT (RTCF)

This bit is set to a “1” after a total power failure. This is a read

only bit that is set by hardware (ISL1221 internally) when the

device powers up after having lost all power to the device. The

bit is set regardless of whether VDD or VBAT is applied first.

The loss of only one of the supplies does not set the RTCF bit

to “1”. The first valid write to the RTC section after a complete

power failure resets the RTCF bit to “0” (writing one byte is

sufficient).

BATTERY BIT (BAT)

This bit is set to a “1” when the device enters battery backup

mode. This bit can be reset either manually by the user or

automatically reset by enabling the auto-reset bit (see “Auto

Reset Enable Bit (ARST)” on page 14). A write to this bit in the

SR can only set it to “0”, not “1”.

ALARM BIT (ALM)

These bits announce if the alarm matches the real time clock. If

there is a match, the respective bit is set to “1”. This bit can be

manually reset to “0” by the user or automatically reset by

enabling the auto-reset bit (see ARST bit). A write to this bit in

the SR can only set it to “0”, not “1”.

NOTE: An alarm bit that is set by an alarm occurring during an SR read

operation will remain set after the read operation is complete.

EVENT DETECT BIT (EVT)

The event detect bit indicates status of the event input pin

(EVIN). When the Event Detect function is enabled and the

EVIN pin is triggered, the EVT bit is set to “1” to indicate a

detection of an event, and the Time Stamp Register records

the current RTC time. A write to this bit in the SR can only set it

to “0” not “1”.

When a HIGH signal is present at the EVIN pin (or a LOW to

HIGH transition), an “event” is detected. On detection the EVT

bit is set HIGH, the open drain EVDET pin is asserted (pulled

LOW), and the RTC time is recorded in the Time Stamp

registers. The EVT bit will be reset to LOW:

• When the EVT bit is set to 0 with a Status Register write

• When there is a read from the Status Register, with the

ARST bit set to “1” (auto-reset enabled).

If the EVT bit has not been cleared, only the initial (first

occurrence) Timestamp is retained in the Timestamp register,

subsequent triggers of the EVIN pin will not record new

timestamps. If the EVT bit is cleared to “0”, the Timestamp

is triggered.

WRITE RTC ENABLE BIT (WRTC)

The WRTC bit enables or disables write capability into the RTC

Timing Registers. The factory default setting of this bit is “0”.

Upon initialization or power up, the WRTC must be set to “1” to

enable the RTC. Upon the completion of a valid write (STOP),

the RTC starts counting. The RTC internal 1Hz signal is

synchronized to the STOP condition during a valid write cycle.

CRYSTAL OSCILLATOR ENABLE BIT (XTOSCB)

This bit enables/disables the internal crystal oscillator. When

the XTOSCB is set to “1”, the oscillator is disabled, and the X1

pin allows for an external 32kHz signal to drive the RTC. The

XTOSCB bit is set to “0” on power up.

TABLE 6. STATUS REGISTER (SR)

ADDR

07h

ARST XTOSCB reserved WRTC

EVT

ALM BAT RTCF

Default

000

ISL1221 Datasheet(PDF) 13 Page - Renesas Technology Corp

ISL1221 Datasheet(HTML) 13 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL