ISL1221 datasheet(21/24 Pages) RENESAS

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ISL1221

FN6316 Rev 1.00

Page 21 of 24

July 15, 2010

Battery Backup Details

The event detection function has been designed to minimize

power drain for extended life in battery backed applications.

Many applications will need detection while in battery backup.

Another bit, the EVBATB bit, is used to control if the event input

is active in battery backup mode. Note that to DISABLE event

sampling in battery backup, this bit is set to 1. The occurrence

of an event is recorded and can be read by the microprocessor

the next time the circuit is powered up. The input current

sources and sampling are also usable in battery backup mode.

If the EVIENB bit is set to disable the input current source, a

large value pullup resistor must be tied to the VBAT input to

allow event detection in battery backup.

Note that any input signal conditioning circuitry that is added in

regular operation or battery backup should have minimum

supply current drain, or have the capability to be put in a low

power standby mode. Op amps such as the EL8176 have low

normal supply current (50µA) and standby power drain (3µA

so can be used in battery backup applications.

Oscillator Crystal Requirements

The ISL1221 uses a standard 32.768kHz crystal. Either

through hole or surface mount crystals can be used. Table 14

lists some recommended surface mount crystals and the

parameters of each. This list is not exhaustive and other

surface mount devices can be used with the ISL1221 if their

specifications are very similar to the devices listed. The crystal

should have a required parallel load capacitance of 12.5pF and

an equivalent series resistance of less than 50k. The crystal’s

temperature range specification should match the application.

Many crystals are rated for -10°C to +60°C (especially through

hole and tuning fork types), so an appropriate crystal should be

selected if extended temperature range is required.

Crystal Oscillator Frequency Adjustment

The ISL1221 device contains circuitry for adjusting the

frequency of the crystal oscillator. This circuitry can be used to

trim oscillator initial accuracy as well as adjust the frequency to

compensate for temperature changes.

The Analog Trimming Register (ATR) is used to adjust the load

capacitance seen by the crystal. There are six bits of ATR

control, with linear capacitance increments available for

adjustment. Since the ATR adjustment is essentially “pulling”

the frequency of the oscillator, the resulting frequency changes

will not be linear with incremental capacitance changes. The

equations which govern pulling show that lower capacitor

values of ATR adjustment will provide larger increments. Also,

the higher values of ATR adjustment will produce smaller

incremental frequency changes. These values typically vary

from 6-10 ppm/bit at the low end to <1ppm/bit at the highest

capacitance settings. The range afforded by the ATR

adjustment with a typical surface mount crystal is typically -34

to +80ppm around the ATR=0 default setting because of this

property. The user should note this when using the ATR for

calibration. The temperature drift of the capacitance used in

the ATR control is extremely low, so this feature can be used

for temperature compensation with good accuracy.

In addition to the analog compensation afforded by the

adjustable load capacitance, a digital compensation feature is

available for the ISL1221. There are 3 bits known as the Digital

Trimming Register (DTR). The range provided is ±60ppm in

increments of 20ppm. DTR operates by adding or skipping

pulses in the clock counter. It is very useful for coarse

adjustments of frequency drift over temperature or extending

the adjustment range available with the ATR register.

Initial accuracy is best adjusted by enabling the frequency

output (using the INT register, address 08h), and monitoring

the FOUT pin with a calibrated frequency counter. The

frequency used is unimportant, although 1Hz is the easiest to

monitor. The gating time should be set long enough to ensure

accuracy to at least 1ppm. The ATR should be set to the center

position, or 100000Bh, to begin with. Once the initial

measurement is made, then the ATR register can be changed

to adjust the frequency. Note that increasing the ATR register

for increased capacitance will lower the frequency, and vice-

versa. If the initial measurement shows the frequency is far off,

it will be necessary to use the DTR register to do a coarse

adjustment. Note that most all crystals will have tight enough

initial accuracy at room temperature so that a small ATR

Temperature Compensation

The ATR and DTR controls can be combined to provide crystal

drift temperature compensation. The typical 32.768kHz crystal

has a drift characteristic that is similar to that shown in Figure

20. There is a turnover temperature (T0) where the drift is very

near 0. The shape is parabolic as it varies with the square of

the difference between the actual temperature and the

turnover temperature.

TABLE 14. SUGGESTED SURFACE MOUNT CRYSTALS

MANUFACTURER

PART NUMBER

Citizen

CM200S

Epson

MC-405, MC-406

Raltron

RSM-200S

SaRonix

32S12

Ecliptek

ECPSM29T-32.768K

ECS

ECX-306

Fox

FSM-327

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