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GMS82524TK Datasheet(PDF) 37 Page - Hynix Semiconductor |
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GMS82524TK Datasheet(HTML) 37 Page - Hynix Semiconductor |
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37 / 93 page ![]() GMS82512/16/24 HYUNDAI MicroElectronics 34 FEB. 2000 Ver 1.00 Figure 11-1 TM0, TM2 Registers BTCL 7654 321 0 T3ST CAP2 T2SL1 INITIAL VALUE: 00H ADDRESS: 0E3H TM2 T2SL0 T2CN T2ST T3SL1 T3SL0 Bit Name Bit Posi- tion Description CAP2 TM2.7 0: Timer/Counter mode 1: Capture mode selection flag T3ST TM2.6 0: When cleared, stop the counting. 1: When set, Timer 3 count register is cleared and start again. T3SL1 T3SL0 TM2.5 TM2.4 00: 16-bit mode (Clock source is selected by T2SL1, T2SL0) 01: 8-bit mode, Clock source is fXIN ÷ 4 10: 8-bit mode, Clock source is fXIN ÷ 16 11: 8-bit mode, Clock source is fXIN ÷ 64 T2ST TM2.3 0: When cleared, stop the counting. 1: When set, Timer 2 Count Register is cleared and start again. T2CN TM2.2 0: Stop the timer 1: A logic 1 starts the timer. T2SL1 T2SL0 TM2.1 TM2.0 00: Reserved 01: 8-bit Timer, Clock source is fXIN ÷ 4 10: 8-bit Timer, Clock source is fXIN ÷ 16 11: 8-bit Timer, Clock source is fXIN ÷ 64 TIMER 2 BT C L 76543210 T1S T C AP0 T 0SL 1 IN IT IA L V A LU E : 00 H AD D R ESS: 0E 2 H TM0 T0S L0 T0C N T0S T T 1 S L1 T 1S L0 Bit Name Bit Position Description CAP0 TM0.7 0: Timer/Counter mode 1: Capture mode selection flag T1ST TM0.6 0: When cleared, stop the counting. 1: When set, Timer 1 count register is cleared and start again. T1SL1 T1SL0 TM0.5 TM0.4 00: 16-bit mode (Clock source is selected by T0SL1, T0SL0) 01: 8-bit mode, Clock source is fXIN ÷ 4 10: 8-bit mode, Clock source is fXIN ÷ 16 11: 8-bit mode, Clock source is fXIN ÷ 64 T0ST TM0.3 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. T0CN TM0.2 0: Stop the timer 1: A logic 1 starts the timer. T0SL1 T0SL0 TM0.1 TM0.0 00: EC0 (External clock) 01: 8-bit Timer, Clock source is fXIN ÷ 4 10: 8-bit Timer, Clock source is fXIN ÷ 16 11: 8-bit Timer, Clock source is fXIN ÷ 64 TIMER 1 TIMER 0 765 43 210 INITIAL VALUE: Undefined ADDRESS: 0E4H ~ 0E7H TDR0~TDR3 Read: Count value read Write: Compare data write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TIMER 3 |
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