GMS82524TK datasheet(55/93 Pages) HYNIX

55 / 93 page

GMS82512/16/24

HYUNDAI MicroElectronics

FEB. 2000 Ver 1.00

activated mode: rising edge, falling edge, and both edge.

Figure 14-7 External Interrupt Block Diagram

INT0 ~ INT3 are multiplexed with general I/O ports

(R40~R43). To use as an external interrupt pin, the bit of

R4 port mode register PMR4 should be set to “1” corre-

spondingly.

Example: To use as an INT0 and INT2

;

**** Set port as an input port R40,R42

LDM

R4DD,#1111_1010B

;

**** Set port as an external interrupt port

LDM

PMR4,#05H

;

**** Set Falling-edge Detection

LDM

IEDS,#0001_0001B

Response Time

The INT0 ~ INT3 edge are latched into INT1IF ~ INT3IF

at every machine cycle. The values are not actually polled

by the circuitry until the next machine cycle. If a request is

active and conditions are right for it to be acknowledged, a

hardware subroutine call to the requested service routine

will be the next instruction to be executed. The DIV itself

takes twelve cycles. Thus, a minimum of twelve complete

machine cycles elapse between activation of an external

interrupt request and the beginning of execution of the first

instruction of the service routine.

Figure 14-8shows interrupt response timings.

Figure 14-8 Interrupt Response Timing Diagram

INT0IF

INT0 pin

INT0 INTERRUPT

INT1IF

INT1 pin

INT1 INTERRUPT

INT2IF

INT2 pin

INT2 INTERRUPT

IEDS

[0F8H]

INT3IF

INT3 pin

INT3 INTERRUPT

Edge selection

Interrupt

goes

active

Interrupt

latched

Interrupt

processing

Interrupt

routine

8 fXIN

max. 12 fXIN

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