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FT29F010B Datasheet(PDF) 9 Page - Force Technologies Ltd

Part # FT29F010B
Description  1 Megabit (128 K x 8-bit) Uniform Sector Flash Memory CMOS 5.0 Volt-only
PDF  30 Pages
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Manufacturer  FORCE [Force Technologies Ltd]
Direct Link   https://www.forcetechnologies.co.uk
Logo FORCE - Force Technologies Ltd

FT29F010B Datasheet(HTML) 9 Page - Force Technologies Ltd

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Table 3.
FT29F010B Autoselect Codes (High Voltage Method)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Description
CE#
OE#
WE#
A16
to
A14
A13
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
DQ7
to
DQ0
Manufacturer ID: Spansion
L
L
H
X
X
VID
X
L
X
L
L
01h
Device ID: FT29F010B
L
L
H
X
X
VID
X
L
X
L
H
20h
Sector Protection Verification
L
L
H
SA
X
VID
X
L
X
H
L
01h
(protected)
00h
(unprotected)
Sector Protection/Unprotection
The hardware sector protection feature dis ables both
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors.
Sector protection/unprotection must be implemented
using programming equipment. The pr ocedure re-
quires a high voltage (VID) on address pin A9 and the
control pins.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or e rasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which mi ght otherwise b e caused by
spurious system level signals during VCC power-up
and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a lo gical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Rev 2
9/30
2014



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