DAC7552 datasheet(16/22 Pages) TI

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Power Down

Asynchronous Clear

IOVDD and Level Shifters

Daisy-Chain Operation

SERIAL INTERFACE

16-Bit Word and Input Shift Register

DAC7552

SLAS442B – JANUARY 2005 – REVISED JUNE 2005

The DAC7552 has a flexible power-down capability

the data is for DAC A, DAC B, or both DACs. Bit 12

as described in Table 2. Individual channels could be

(DB12)

determines

either

normal

mode

powered down separately or all channels could be

power-down mode (see Table 2). All channels are

powered down simultaneously. During a power-down

updated when bits 15 and 14 (DB15 and DB14) are

condition, the user has flexibility to select the output

high.

impedance of each channel. During power-down

operation, each channel can have either 1-k

Ω,

The SYNC input is a level-triggered input that acts as

100-k

Ω, or Hi-Z output impedance to ground.

a frame synchronization signal and chip enable. Data

can only be transferred into the device while SYNC is

low. To start the serial data transfer, SYNC should be

taken low, observing the minimum SYNC to SCLK

The DAC7552 output is asynchronously set to

falling edge setup time, t4. After SYNC goes low,

zero-scale voltage immediately after the CLR pin is

serial data is shifted into the device's input shift

brought low. The CLR signal resets all internal

registers and therefore behaves like the Power-On

pulses.

Reset. The DAC7552 updates at the first rising edge

of the SYNC signal that occurs after the CLR pin is

When DCEN is low, SDO pin is brought to a Hi-Z

brought back to high.

state. The first 16 data bits that follow the falling edge

of SYNC are stored in the shift register. The rising

edge of SYNC that follows the 16th data bit updates

the DAC(s). If SYNC is brought high before the 16th

The DAC7552 can be used with different logic famil-

data bit, no action occurs.

ies that require a wide range of supply voltages (from

1.8 V to 5.5 V). To enable this useful feature, the

When DCEN is high, data can continuously be shifted

IOVDD pin must be connected to the logic supply

into the shift register, enabling the daisy-chain oper-

voltage of the system. All DAC7552 digital input and

ation. SDO pin becomes active and outputs SDIN

output pins are equipped with level-shifter circuits.

data with 16 clock cycle delay. A rising edge of SYNC

Level shifters at the input pins ensure that external

loads the shift register data into the DAC(s). The

logic high voltages are translated to the internal logic

loaded data consists of the last 16 data bits received

high voltage, with no additional power dissipation.

into the shift register before the rising edge of SYNC.

Similarly, the level shifter for the SDO pin translates

If daisy-chain operation is not needed, DCEN should

the internal logic high voltage (AVDD) to the external

permanently be tied to a logic low voltage.

logic high level (IOVDD). For single-supply operation,

the IOVDD pin can be tied to the AVDD pin.

When DCEN pin is brought high, daisy chaining is

enabled. Serial Data Output (SDO) pin is provided to

The DAC7552 is controlled over a versatile 3-wire

daisy-chain multiple DAC7552 devices in a system.

serial interface, which operates at clock rates up to

50 MHz and is compatible with SPI, QSPI, Microwire,

As long as SYNC is high or DCEN is low, the SDO

and DSP interface standards.

pin is in a high-impedance state. When SYNC is

brought low the output of the internal shift register is

In daisy-chain mode (DCEN = 1), the DAC7552

tied to the SDO pin. As long as SYNC is low and

requires a falling SCLK edge after the rising SYNC, in

DCEN is high, SDO duplicates SDIN signal with a

order to initialize the serial interface for the next

16-cycle delay. To support multiple devices in a daisy

update.

chain, SCLK and SYNC signals are shared across all

devices, and SDO of one DAC7552 should be tied to

the SDIN of the next DAC7552. For n devices in such

a daisy chain, 16n SCLK cycles are required to shift

The input shift register is 16 bits wide. DAC data is

the entire input data stream. After 16n SCLK falling

loaded into the device as a 16-bit word under the

edges are received, following a falling SYNC, the

control of a serial clock input, SCLK, as shown in the

data stream becomes complete and SYNC can be

Figure 1 timing diagram. The 16-bit word, illustrated

brought high to update n devices simultaneously.

in Table 1, consists of four control bits followed by 12

SDO operation is specified at a maximum SCLK

bits of DAC data. The data format is straight binary

speed of 10 MHz.

with all zeroes corresponding to 0-V output and all

ones corresponding to full-scale output (VREF – 1

LSB). Data is loaded MSB first (bit 15) where the first

two bits (DB15 and DB14) determine if the input

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