M30102 datasheet(49/164 Pages) RENESAS

49 / 164 page

Under

development

Tentative Specifications REV.E1

Specifications in this manual are tentative and subject to change.

Mitsubishi microcomputers

M30100/M30102 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupts

Returning from an Interrupt Routine

Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register

(FLG) as it was immediately before the start of interrupt sequence and the contents of the program

counter (PC), both of which have been saved in the stack area. Then control returns to the program that

was being executed before the acceptance of the interrupt request, so that the suspended process re-

sumes.

Return the other registers saved by software within the interrupt routine using the POPM or similar in-

struction before executing the REIT instruction.

Interrupt Priority

If there are two or more interrupt requests occurring at a point in time within a single sampling (checking

whether interrupt requests are made), the interrupt assigned a higher priority is accepted.

Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority

level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher

hardware priority is accepted.

Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),

watchdog timer interrupt, etc. are regulated by hardware.

Figure 1.12.8 shows the priorities of hardware interrupts.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches

invariably to the interrupt routine.

Interrupt Priority Level Judge Circuit

This circuit selects the interrupt with the highest priority level when two or more interrupts are generated

simultaneously.

Figure 1.12.9 shows the interrupt resolution circuit.

M30102 Datasheet(PDF) 49 Page - Renesas Technology Corp