M30102 datasheet(13/164 Pages) RENESAS

13 / 164 page

Under

development

Tentative Specifications REV.E1

Specifications in this manual are tentative and subject to change.

Mitsubishi microcomputers

M30100/M30102 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CPU

• Bit 7: Stack pointer select flag (U flag)

Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected

when this flag is “1”.

_______

This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software

interrupt Nos. 0 to 31 is executed.

• Bits 8 to 11: Reserved area

• Bits 12 to 14: Processor interrupt priority level (IPL)

Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight

processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt

is enabled.

• Bit 15: Reserved area

The C, Z, S, and O flags are changed when instructions are executed. See the software manual for

details.

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

Reserved area

Flag register (FLG)

IPL

b15

Figure 1.4.2. Flag register (FLG)

M30102 Datasheet(PDF) 13 Page - Renesas Technology Corp