LTC1743 datasheet(14/24 Pages) LINER

14 / 24 page

LTC1743

1743f

APPLICATIO S I FOR ATIO

Common Mode Bias

The ADC sample-and-hold circuit requires differential drive

to achieve specified performance. Each input should swing

±0.8Vforthe3.2Vrangeor±0.5Vforthe2Vrange,around

a common mode voltage of 2.5V. The VCM output pin

(Pin 2) may be used to provide the common mode bias

level. VCM can be tied directly to the center tap of a trans-

former to set the DC input level or as a reference level to

an op amp differential driver circuit. The VCM pin must be

bypassed to ground close to the ADC with 4.7

µForgreater.

Input Drive Impedance

As with all high performance, high speed ADCs the dy-

namic performance of the LTC1743 can be influenced by

the input drive circuitry, particularly the second and third

harmonics. Source impedance and input reactance can

influence SFDR. At the falling edge of encode the sample-

and-hold circuit will connect the 7pF sampling capacitor to

the input pin and start the sampling period. The sampling

period ends when encode rises, holding the sampled input

on the sampling capacitor. Ideally the input circuitry

should be fast enough to fully charge the sampling capaci-

tor during the sampling period 1 / (2Fencode); however,

this is not always possible and the incomplete settling may

degrade the SFDR. The sampling glitch has been designed

to be as linear as possible to minimize the effects of

incomplete settling.

For the best performance, it is recomended to have a

source impedence of 100

Ω or less for each input. The

source impedence should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

Input Drive Circuits

Figure 3 shows the LTC1743 being driven by an RF

transformer with a center tapped secondary. The second-

ary center tap is DC biased with VCM, setting the ADC input

signal at its optimum DC level. Figure 3 shows a 1:1 turns

ratio transformer. Other turns ratios can be used if the

source impedence seen by the ADC does not exceed

100

Ω for each ADC input. A disadvantage of using a

transformer is the loss of low frequency response. Most

small RF transformers have poor performance at frequen-

cies below 1MHz.

1:1

Ω

0.1

µF

ANALOG

INPUT

VCM

AIN

–

100

Ω

100

Ω

18pF

1743 F03

4.7

µF

Ω

LTC1743

Figure 3. Single-Ended to Differential

Conversion Using a Transformer

LTC1743 Datasheet(PDF) 14 Page - Linear Technology

LTC1743 Datasheet(HTML) 14 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL