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LTC1743

1743f

LTC1743

1743 F09

OVDD

VDD

0.1

µF

Ω

TYPICAL

DATA

OUTPUT

OGND

OVDD

0.5V TO

VDD

PREDRIVER

LOGIC

DATA

FROM

LATCH

Maximum and Minimum Encode Rates

The maximum encode rate for the LTC1743 is 50Msps. For

the ADC to operate properly the encode signal should have

a 50% (

±5%) duty cycle. Each half cycle must have at least

9.5ns for the ADC internal circuitry to have enough settling

time for proper operation. Achieving a precise 50% duty

cycle is easy with differential sinusoidal drive using a

transformer or using symmetric differential logic such as

PECL or LVDS. When using a single-ended encode signal

asymmetric rise and fall times can result in duty cycles that

are far from 50%.

At sample rates slower than 50Msps the duty cycle can

vary from 50% as long as each half cycle is at least 9.5ns.

The lower limit of the LTC1743 sample rate is determined

by the droop of the sample-and-hold circuits. The pipelined

architecture of this ADC relies on storing analog signals

on small valued capacitors. Junction leakage will dis-

charge the capacitors. The specified minimum operating

frequency for the LTC1743 is 1Msps.

DIGITAL OUTPUTS

Digital Output Buffers

Figure 9 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OVDD and OGND, iso-

lated from the ADC power and ground. The additional

N-channel transistor in the output driver allows operation

down to low voltages. The internal resistor in series with

the output makes the output appear as 50

Ω to external

circuitry and may eliminate the need for external damping

resistors.

Output Loading

As with all high speed/high resolution converters the

digital output loading can affect the performance. The

digital outputs of the LTC1743 should drive a minimal

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. The output

should be buffered with a device such as an ALVCH16373

CMOS latch. For full speed operation the capacitive load

should be kept under 10pF. A resistor in series with the

output may be used but is not required since the ADC has

a series resistor of 43

Ω on chip.

Lower OVDD voltages will also help reduce interference

from the digital outputs.

Format

The LTC1743 parallel digital output can be selected for

offset binary or 2’s complement format. The format is

selected with the MSBINV pin; high selects offset binary.

Overflow Bit

An overflow output bit indicates when the converter is

overranged or underranged. When OF outputs a logic high

the converter is either overranged or underranged.

APPLICATIO S I FOR ATIO

Figure 9. Equivalent Circuit for a Digital Output Buffer

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