THS10082

SLAS254B – MAY 2002 – REVISED NOVEMBER 2002

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28

PARAMETER

MIN

TYP

MAX

UNIT

tsu(R/W)

Setup time, R/W high to last CS valid

0

ns

ta

Access time, last CS valid to data valid

0

10

ns

td(CSDAV) Delay time, last CS valid to DATA_AV inactive

12

ns

th

Hold time, first CS invalid to data invalid

0

5

ns

th(R/W)

Hold time, first external CS invalid to R/W change

5

ns

tw(CS)

Pulse duration, CS active

10

ns

(1) CS = CS0

Write Timing (Using R/W, CS0-Controlled)

Figure 37 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W.

The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last

external signal of CS0, CS1, and R/W which becomes valid.

90%

90%

90%

10%

tw(CS)

tsu(R/W)

th(R/W)

CS0

CS1

WR

RD

D(0–9)

DATA_AV

10%

tsu

th

Figure 37. Write Timing Diagram Using R/W (CS0-controlled)

PARAMETER

MIN

TYP

MAX

UNIT

tsu(R/W)

Setup time, R/W stable to last CS valid

0

ns

tsu

Setup time, data valid to first CS invalid

5

ns

th

Hold time, first CS invalid to data invalid

2

ns

th(R/W)

Hold time, first CS invalid to R/W change

5

ns

tw(CS)

Pulse duration, CS active

10

ns

(1) CS = CS0