TPS5300

SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001

9

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Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

ANAGND

4

Analog ground

BG

17

O

Bottom gate drive. BG is an output drive to the low-side synchronous rectifier FET.

BOOT

21

I

Bootstrap. Connect a 1-

µF low-ESR ceramic capacitor to PH to generate a floating drive for the high-side

FET driver.

DROOP

10

I

Active voltage droop position voltage. DROOP is a voltage input used to set the amount of output-voltage,

set-point droop as a function of load current. The amount of droop compensation is set with a resistor divider

between IOUT and ANAGND. A voltage divider from VO to VSENSE_CORE sets the no-load offset.

DRV_CLK

1

O

CLK voltage regulator. DRV_CLK drives an external NPN bipolar power transistor for regulating CLK

voltage to VREF_CLK.

DRVGND

16

Drive ground. Ground for FET drivers. Connect to FET PWRGND

DRV_IO

32

O

Drives an external NPN bipolar power transistor for regulating IO voltage to VREF_IO.

DT_SET

3

I

DT_SET sets the transition time for speed step output voltage positioning. Attach a capacitor from DT_SET

to ground to program time.

ENABLE_EXT

29

O

Open drain output. ENABLE_EXT enables the external converters when the internal enable signal is high

(good), and disables when there is a fault with any regulator (OVP, UVP, OCPrr), VR_ON UVLO is low, or the

VBIAS UVLO is low. Can be connected to the enable terminal of an external linear regulator or switching

controller. A pullup resistor is required to set the desired voltage rail.

IS–

13

I

Current sense negative Kelvin connection. Connect to the node between the current sense resistor and the

output capacitors. Keep the PCB trace short and route trace next to the IS+ trace to help reduce loop

inductance noise pickup and cancel common mode noise through mutual coupling.

IS+

14

I

Current sense positive Kelvin connection. Connect to the node between the output inductor and the current

sense resistor. Keep the PCB trace short and route trace next to the IS-trace to help reduce loop inductance

noise and cancel common mode noise through mutual coupling.

IOUT

11

O

Current sense differential amplifier output. The voltage on IOUT equals

25 x (VI(+) – VI(–)) = 25 x (R(sense) xIL).

OCP

9

I

Overcurrent protection. Current limit trip point is set with a resistor divider between IOUT and ANAGND. The

typical OCP trip point should be set at 1.30

×I(max).TheOCPvoltagealsosetsthePSMautomatictrippoints.

PH

19

I/O

Phase voltage node. PH is used for bootstrap low reference. PH connects to the junction of the high-side and

low-side FET’s.

PSM/LATCH

12

I

PSM. Power saving mode boosts efficiency at low-load current by automatically decreasing the switching

frequency toward the natural converter operating frequency. A logic low (<1.8) disables PSM, maintaining

the higher switching frequency range set by ramp components. See Figure 1.

LATCH. Allows disabling fault latch. Recommend enabling fault latch protection

RAMP

28

I/O

Sets a ramp on the feedback signal to increase the switching frequency. Add a resistor from PH to RAMP and

connect RAMP to VSENSE_CORE for a dc-coupled ramp. Add a capacitor from RAMP to VSENSE_CORE

to set an ac-coupled ramp.

SLOWST

6

I

Slowstart (softstart). A capacitor from SLOWST to GND sets the slowstart time for the ripple regulator and

the two linear regulators. The three converters will ramp up together while tracking the output voltage. A

current equal to I(VREFB)/5 charges the capacitor.

TG

20

O

Top gate drive. TG is an output drive to the high-side power switching FET’s. It is also used in the

anticross-conduction circuit to eliminate shoot-through current.

VBIAS

30

I

Analog VBIAS. It is recommended that at least a 1-

µF capacitor be connected to ANAGND. Supply from VCC

through RC filter

VCC

18

Supply voltage. VCC is the supply voltage for the FET drivers. Add an external resistor/capacitor filter from

VCC to VBIAS. It is recommended that a 1-

µF capacitor be connected to the DRVGND terminal.

VGATE

15

O

Logical and output of the combined core, IO, and CLK powergood. VGATE outputs a logic high when all

(core, IO, CLK) output voltages are within 7% of the reference voltage. An open drain output allows setting to

desired voltage level through a pullup resistor.