TPS5300

SLVS334A – DECEMBER 2000 – REVISED SEPTEMBER 2001

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detailed description (continued)

low-side driver

high-side driver

2-A source and 3.3-A sink. The high-side driver is configured as a floating bootstrap driver. The internal

bootstrap diode, connected between the DRV and BOOT pins, is a Schottky diode for improved drive efficiency.

The maximum voltage that can be applied between the BOOT pin and ground is 35 V.

deadtime control

The deadtime control prevents shoot-through current from flowing through the main power FET’s during the

switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side driver is not

allowed to turn on until the gate drive voltage to the low-side FET is below 1.7 V. The low-side driver is not

allowed to turn on until the gate drive voltage from the high-side FET to PH is below 1.3 V.

current sensing

Current sensing is achieved by sensing the voltage across a current-sense resistor placed in series between

the output inductor and the output capacitors. The sensing network consists of a high bandwidth differential

amplifier with a gain of 25x to allow using sense resistors with values as low as 1 m

Ω. Sensing occurs at all times

to allow having real-time information for quick response during an active voltage droop positioning transition.

The voltage on the IOUT pin equals 25 times the sensed voltage.

VR_ON

The VR_ON terminal is a TTL compatible digital pin that is used to enable the controller. When VR_ON is low,

the output drivers are low, the linear regulator drivers are off, and the slowstart capacitor is discharged. When

VR_ON goes high, the short across the slowstart capacitor is released and normal converter operation begins.

When the system logic supply is connected to the VR_ON pin, the VR_ON pin can control power sequencing

by locking out controller operation until the system logic supply exceeds the input threshold voltage of the

before the controller is allowed to start up. Likewise, a microprocessor or other external logic can also control

the sequencing through VR_ON.

The VBIAS undervoltage-lockout circuit disables the controller, while VBIAS is below the 4.46-V start threshold

during power up. The controller is disabled when VBIAS goes below 3.3 V. While the controller is disabled, the

output drivers will be low and the slowstart capacitor will be shorted. When VBIAS exceeds the start threshold,

the short across the slowstart capacitor is released and normal converter operation begins.

IO linear regulator driver

The IO linear regulator driver circuit drives a high power NPN external power transistor, allowing external power

dissipation. The IO voltage is ramped up with the slowstart with the other two converters. Under voltage

protection protects against hard shorts or extreme loading. The VSENSE_IO voltage is monitored by the VGATE

(powergood) circuit. A fault or shutdown on any converter will shut down the linear regulator.

CLK linear regulator driver

The CLK linear regulator driver circuit drives a lower power NPN external power transistor, allowing external

power dissipation. The CLK voltage is ramped up with the slowstart with the other two converters. Under voltage

protection protects against hard shorts or extreme loading. The VSENSE_CLK voltage is monitored by the

VGATE (powergood) circuit. A fault or shutdown on any converter will shut down the linear regulator.