APA3175 datasheet(13/46 Pages) ANPEC

13 / 46 page

Rev. A.3 - Aug., 2016

www.anpec.com.tw

APA3175

Function Description

Clock And PLL

The APA3175 is a slave device and receives signals from MCLK, SCLK, and LRCLK. The digital audio processor

(DAP) provides all sample rates and MCLK rates which defined in the clock control register.

The APA3175 checks to verify that SCLK is a particular value of 32f

S, 48fS, or 64fS. The DAP only provides a 1×fS LRCLK.

The timing relationship of these clocks to SDIN is shown in subsequent sections.

Serial Data Interface

Serial data is an input transmitted to SDIN. The PWM outputs are derived from SDIN. Besides, the APA3175 DAP

receives left-justified, right-justified, and I2S serial data formats with 16, 20, or 24 bit.

PWM Section

The APA3175 DAP device is a high power efficiency and high-performance digital audio reproduction. A noise shaper

is used to increase dynamic range and SNR in the audio band. The PWM section receives 24bit PCM data from the

DAP and outputs two BTL PWM audio output channels.

The PWM section has individual channel dc blocking filters that can be enabled and disabled. The low pass filter cutoff

frequency is less than 1Hz. Besides, the PWM section includes individual channel de-emphasis filters for 44.1 and 48

kHz and can be enabled and disabled.

The adjustable maximum modulation limit of PWM section is from 93.8% to 98.4%.

I2C Compatible Serial Control Interface

The APA3175 DAP receives commands from a system controller through an I2C serial control slave interface. The

serial control interface supports both normal-speed 100kHz and high-speed 400kHz operations without waiting

states. As an added feature, even though the MCLK is absent, the interface operates.

For status registers, the serial control interface provides both single-byte and multi-byte read and write operations;

and for the general control registers, they associated with the PWM.

APA3175 Datasheet(PDF) 13 Page - Anpec Electronics Coropration