© 2007 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FSSD07 Rev. 1.0.2

4

Functional Description

The FSSD07 enables the multiplexing of dual ASIC /

baseband processor hosts to a common peripheral card

or module, providing bi-directional support of the dual-

voltage SD/SDIO or MMC cards available in the

marketplace. Each host SDIO port has its own supply

rail, such that hosts with different supplies can be

interfaced to a common peripheral module or card. The

peripheral card supply must be equal to or greater than

the host(s) to minimize power consumption. The

supplies

connected

from

the

application

Power

Management ICs (PMICs) to the FSSD07. The clock

path is a uni-directional buffered path rather than a bi-

3M

) to ensure the supply rails internally do not float if

the application turns off one or all of these sources.

CMD, DAT Bus Pull-ups

The CMD and DAT[3:0] ports do not have, internally, the

system pull-up resistors as defined in the MMC or SD

card system bus specifications. The system bus pull-up

must be added external to the FSSD07. The value,

within the specific specification limits, is a function of the

individual application and type of card or peripheral

pull-ups should be between 10k

Ω and 100kΩ. For MMC

4.7k

Ω and 100kΩ, and the R

Ω

and 100k

Ω. The card-side CMD and DAT[3:0] outputs

have a circuit that facilitates incident wave switching, so

the external pull-up resistors ensure retention of the

output high level.

The OE pin can be used to place the CMD and DAT[3:0]

into high-impedance mode during power-up sequencing

or when the system enters IDLE state (see IDLE State

CMD/DAT Bus “Parking”

).

CLK Bus

The

1CLK

and

2CLK

inputs

are

bi-state

buffer

architectures, rather than a switch I/O, to ensure 52MHz

incident wave switching. Since most host controllers

also have a clock enable register bit to enable or disable

the system clock when in IDLE mode, the CLK output is

not disabled by the OE pin. Instead, the CLK output is a

function of whichever host controller clock is selected by

the S pin.

Consequently, there is always a clock path connected

between the selected host and the card. The state of the

CLK pin is a function of the selected host controller

nCLK output pin, which facilitates retaining clock duty

cycle in the system or performing read / wait operations.

IDLE State & Power-Up CMD/DAT Bus

“Parking”

The SD and MMC card specifications were written for a

direct

point-to-point

communication

between

host

controller and card. The introduction of the FSSD07 in

that path, as an expander, requires that the functional

operation and system latency not be impacted by the

switch characteristics. Since there are various card

formats, protocols, and configurable controllers, an OE

pin is available to facilitate a fast IDLE transition for the

CMD/DAT[3:0] outputs. Some controllers, rather than

placing CMD/DAT into high-impedance mode, pull the

outputs HIGH for a clock cycle prior to going into high-

impedance mode (referred to as “parking” the output).

Some legacy controllers pull their outputs HIGH versus

high impedance.

If the OE pin is pulled HIGH and the controller places its

command and data outputs into high-impedance (driving

nCMD/nDAT[3:0]), the FSSD07 CMD/DAT[3:0] output

rise time is a function of the RC time constant through

the switch path. Pulling OE LOW puts the switches into

high impedance, disabling communication from the host

to card, and the CMD/DAT[3:0] outputs are pulled HIGH

by

the

system

pull-up

resistors

chosen

for

the

application.

This

mechanism

facilitates

power-up

sequencing by holding OE LOW until supplies are stable

and communication between the host(s) and card is

enabled.

Power Optimization

consumption,

current

paths between supplies are

isolated when one or more supplies are not present.

with host controller supplies remaining present.