FUSB303 datasheet(12/19 Pages) ONSEMI

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FUSB303

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Table 11. FAST MODE I2C TIMING SPECIFICATIONS (see Figure 7)

Symbol

Parameter

Fast Mode

Min.

Max.

Unit

fSCL

SCL/OUT2 Clock Frequency

400

kHz

tHD;STA

Hold Time (Repeated) START Condition

0.6

tLOW

Low Period of SCL/OUT2 Clock

1.3

tHIGH

High Period of SCL/OUT2 Clock

0.6

tSU;STA

Set−up Time for Repeated START Condition

0.6

tHD;DAT

Data Hold Time

0.9

tSU;DAT

Data Set−up Time (Note 5)

100

Rise Time of SDA/OUT1 and SCL/OUT2 Signals (Note 6)

×(VDD/5.5 V)

250

Fall Time of SDA/OUT1 and SCL/OUT2 Signals (Note 6)

×(VDD/5.5 V)

250

tSU;STO

Set−up Time for STOP Condition

0.6

tBUF

Bus−Free Time between STOP and START Conditions

1.3

tSP

Pulse Width of Spikes that Must Be Suppressed by the Input Filter

A fast−mode I2C−bus device can be used in a standard−mode I2C−bus

system, but the requirement tSU;DAT

≥ 250 ns must be met. This is

automatically the case if the device does not stretch the LOW period of the

SCL/OUT2 signal. If such a device does stretch the LOW period of the

SCL/OUT2 signal, it must output the next data bit to the I2C_ line tr_max +

tSU;DAT = 1000 + 250 = 1250 ns (according to the standard−mode I2C bus

specification) before the SCL/OUT2 line is released

Cb equals the total capacitance of one bus line in pF. If mixed with high−speed devices, faster fall times are allowed according to the I2C

specification

SDA

SCL

LOW

HD;STA

HD;DAT

HIGH

SU;DAT

SU;STA

HD;STA

SU;STO

BUF

Figure 7. Definition of Timing for Full/Speed Mode Devices on the I2C Bus

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