LTC6955 datasheet(14/22 Pages) AD

14 / 22 page

LTC6955

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Figure 4. Block Diagram for LTC6955 Design Example

LTC6955 Design Example with Eight ADCs

This design example consists of a system of eight analog-

to-digital converters (ADCs) being driven from a single

LTC6955. Assume PCB layout constraints require four

ADCs on the top of the circuit board and four on the bot-

tom. This means the LTC6955 should ideally provide four

non-inverted clocks for the topside ADCs and four inverted

clocks for the bottom side ADCs. Referring to Table 2, SEL

code 9 provides the closest number and polarity of active

outputs, even though one spare output will be active.

Figure 4 shows a block diagram of the proposed system.

Note that any active output should be terminated with

100Ω, even if it is not used.

30Ω

75Ω

0.1µF

500MHz OSCILLATOR

OR VCO

+ –

–

ADC0

LTC6955

PCB TOP

CLK

PCB TOP

–

100Ω

MAY BE ROUTED INTO

VCO INPUT OF LTC6952

FOR CLOSED LOOP

PHASE LOCKING OF VCO.

FILT

SEL0

SEL1

SEL2

SEL3

V+

6955 F04

–

OUT0

+ –

OUT1

–

OUT2

OUT3

INV

–

OUT4

–

OUT5

INV

–

OUT6

100Ω

OUT10

–

OUT9

INV

–

OUT8

–

OUT7

INV

ADC1

–

CLK

PCB BOTTOM

ADC2

CLK

PCB TOP

–

ADC3

–

CLK

PCB BOTTOM

ADC4

CLK

PCB TOP

–

100Ω

ADC5

–

CLK

PCB BOTTOM

100Ω

ADC6

CLK

PCB TOP

–

100Ω

ADC7

–

CLK

PCB BOTTOM

For this example, assume the input is being driven sin-

gle-ended by a 500MHz sine wave oscillator with output

swing of 1.6VP-P. The incoming slew rate (SR) can be

determined from the following equation:

SR = VAMP • 2π • fIN

where VAMP is the input amplitude (in VP) and fIN is the

input frequency (in Hz). In this example:

SR = 0.8VP • 2π • 500MHz = 2.5V/ns

Referring to Table 1, set the FILT pin to GND since 2.5V/ns

is greater than 2V/ns.

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